參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 19/82頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 26 of 82
March 20, 2007 – Revision 1.01
Leaves unchanged the function number and register number fields.
The bridge asserts a unique address line based on the device number. These address lines may be used
as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the
Type 1 address bits P_AD[15:11]. presents the mapping that the bridge uses.
Table 2-6. Device Number to IDSEL S_AD Pin Mapping
Device Number
P_AD[15:11]
Secondary IDSEL S_AD[31:16]
S_AD
0h
00000
0000 0000 0000 0001
16
1h
00001
0000 0000 0000 0010
17
2h
00010
0000 0000 0000 0100
18
3h
00011
0000 0000 0000 1000
19
4h
00100
0000 0000 0001 0000
20
5h
00101
0000 0000 0010 0000
21
6h
00110
0000 0000 0100 0000
22
7h
00111
0000 0000 1000 0000
23
8h
01000
0000 0001 0000 0000
24
9h
01001
0000 0010 0000 0000
25
Ah
01010
0000 0100 0000 0000
26
Bh
01011
0000 1000 0000 0000
27
Ch
01100
0001 0000 0000 0000
28
Dh
01101
0010 0000 0000 0000
29
Eh
01110
0100 0000 0000 0000
30
Fh
01111
1000 0000 0000 0000
31
10h – 1Eh
10000 – 11110
0000 0000 0000 0000
-
1Fh
11111
Generate special cycle (P_AD[7:2] > 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
-
The bridge can assert up to 16 unique address lines to be used as IDSEL signals for
up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of
electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary.
However, if device numbers greater than 15 are desired, some external method of generating IDSEL
lines must be used, and no upper address bits are then asserted. The configuration transaction is still
translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a
secondary device, the transaction ends in a master abort.
The bridge forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions.
Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
2.7.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or
more levels of PCI-to-PCI bridges are used.
When the bridge detects a Type 1 configuration transaction intended for a PCI bus downstream from
the secondary bus, the bridge forwards the transaction unchanged to the secondary bus. Ultimately, this
transaction is translated to a Type 0 configuration command or to a special cycle transaction by a
downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following
conditions are met during the address phase:
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus
number register and the upper limit (inclusive) in the subordinate bus number register.
07-0067
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