參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 57/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 60 of 82
March 20, 2007 – Revision 1.01
31 – 24
23 – 16
15 – 8
7 – 0
DWORD ADDRESS
Reserved
Miscellaneous
Control
Reserved
C0h
Reserved
C4h - FFh
13.2.1 VENDOR ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
15:0
Vendor ID
RO
Identifies Pericom as the vendor of this device. Hardwired as 12D8h.
13.2.2 DEVICE ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
31:16
Device ID
RO
Identifies this device as the PI7C8140A. Reset to 8140h.
13.2.3 COMMAND REGISTER – OFFSET 04h
Bit
Function
Type
Description
0
I/O Space
Enable
RW
0: ignore I/O transactions on the primary interface
1: enable response to I/O transactions on the primary interface
Reset to 0
1
Memory Space
Enable
RW
0: ignore memory transactions on the primary interface
1: enable response to memory transactions on the primary interface
Reset to 0
2
Bus Master
Enable
RW
0: do not initiate memory or I/O transactions on the primary interface and disable
response to memory and I/O transactions on the secondary interface
1: enables bridge to operate as a master on the primary interfaces for memory and
I/O transactions forwarded from the secondary interface
Reset to 0
3
Special Cycle
Enable
RO
No special cycles defined.
Bit is defined as read only and returns 0 when read
4
Memory Write
And Invalidate
Enable
RO
Bridge does not generate memory write and invalidate transactions except for
forwarding a transaction for another master.
Bit is implemented as read only and returns 0 when read (unless forwarding a
transaction for another master)
5
VGA Palette
Snoop Enable
RW
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the primary
interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive
of ISA alias; AD[15:10] are not decoded and may be any value)
Reset to 0
6
Parity Error
Response
RW
0: bridge may ignore any parity errors that it detects and continue normal
operation
1: bridge must take its normal action when a parity error is detected
Reset to 0
07-0067
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