參數(shù)資料
型號: PI7C8140AMAE
廠商: Pericom
文件頁數(shù): 55/82頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝: 39
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 59 of 82
March 20, 2007 – Revision 1.01
13
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte DWORD to define various attributes of PI7C8140A as shown
below.
13.1 REGISTER TYPES
REGISTER TYPE
DEFINITION
RO
Read Only
RW
Read / Write
RWC
Read / Write 1 to Clear
RWR
Read / Write 1 to Reset (for about 20 clocks)
RWS
Read / Write 1 to Set
13.2 CONFIGURATION REGISTER
31 – 24
23 – 16
15 – 8
7 – 0
DWORD ADDRESS
Device ID
Vendor ID
00h
Primary Status
Command
04h
Class Code
Revision ID
08h
Reserved
Header Type
Primary Latency
Timer
Cache Line Size
0Ch
Reserved
10h – 14h
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus
Number
18h
Secondary Status
I/O Limit Address
I/O Base Address
1Ch
Memory Limit Address
Memory Base Address
20h
Prefetchable Memory Limit Address
Prefetchable Memory Base Address
24h
Prefetchable Memory Base Address Upper 32-bit
28h
Prefetchable Memory Limit Address Upper 32-bit
2Ch
I/O Limit Address Upper 16-bit
I/O Base Address Upper 16-bit
30h
Reserved
Capability Pointer
34h
Reserved
38h
Bridge Control
Interrupt Pin
Interrupt Line
3Ch
Subsystem ID
Subsystem Vendor ID
40h
Arbiter Control
Diagnostic / Chip Control
44h
Reserved
Extended Chip Control
48h
Secondary Bus
Arbiter Preemption
Control
Reserved
4Ch
Reserved
50h – 60h
Reserved
P_SERR# Event
Disable
64h
Reserved
P_SERR# Status
Secondary Clock Control
68h
CLKRUN
Reserved
6Ch
Reserved
70h
Reserved
Port Option
74h
Reserved
78h – 7Ch
Power Management Capabilities
Next Item Pointer
Capability ID
80h
Reserved
Power Management Data
84h
Secondary Master Timeout Counter
Primary Master Timeout Counter
88h
Reserved
8Ch
Reserved
HSCSR
Next Item Pointer
Capability ID
90h
Reserved
Hot Swap Switch
94h
Reserved
98h – BFh
07-0067
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