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參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 26/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 32 of 82
March 20, 2007 – Revision 1.01
Use more than 16 clocks to accept this transaction.
For delayed read transactions:
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a posted write
transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been queued.
A locked sequence is being propagated across the bridge, and the read transaction is not a locked
transaction.
The bridge is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For posted write transactions:
The posted write data buffer does not have enough space for address and at least one DWORD of
write data.
A locked sequence is being propagated across the bridge, and the write transaction is not a locked
transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the
transaction with the same address and bus command as well as the data if it is a write transaction,
within the time frame specified by the master timeout value. Otherwise, the transaction is discarded
from the buffers.
2.8.4.2 TARGET DISCONNECT
The bridge returns a target disconnect to an initiator when one of the following conditions is met:
Bridge hits an internal address boundary.
Bridge cannot accept any more write data.
Bridge has no more read data to deliver.
See Section 2.5.4 for a description of write address boundaries, and Section 2.6.4 for a description of
read address boundaries.
2.8.4.3 TARGET ABORT
The bridge returns a target abort to an initiator when one of the following conditions is met:
The bridge is returning a target abort from the intended target.
When the bridge returns a target abort to the initiator, it sets the signaled target abort bit in the
status register corresponding to the initiator interface.
07-0067
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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