參數(shù)資料
型號(hào): PI7C8140AMAE
廠商: Pericom
文件頁(yè)數(shù): 59/82頁(yè)
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝: 39
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 62 of 82
March 20, 2007 – Revision 1.01
13.2.5 REVISION ID REGISTER – OFFSET 08h
Bit
Function
Type
Description
7:0
Revision
RO
Indicates revision number of device. Hardwired to 00h
13.2.6 CLASS CODE REGISTER – OFFSET 08h
Bit
Function
Type
Description
15:8
Programming
Interface
RO
Read as 00h to indicate no programming interfaces have been defined for PCI-to-
PCI bridges
23:16
Sub-Class Code
RO
Read as 04h to indicate device is PCI-to-PCI bridge
31:24
Base Class
Code
RO
Read as 06h to indicate device is a bridge device
13.2.7 CACHE LINE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
7:0
Cache Line
Size
RW
Designates the cache line size for the system and is used when terminating
memory write and invalidate transactions and when prefetching memory read
transactions.
Only cache line sizes (in units of 4-byte) which are a power of two are valid (only
one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid
values).
Reset to 0
13.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
15:8
Primary
Latency timer
RW
This register sets the value for the Master Latency Timer, which starts counting
when the master asserts FRAME#.
Reset to 0
13.2.9 HEADER TYPE REGISTER – OFFSET 0Ch
Bit
Function
Type
Description
23:16
Header Type
RO
Read as 01h to indicate that the register layout conforms to the standard PCI-to-
PCI bridge layout.
13.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h
Bit
Function
Type
Description
7:0
Primary Bus
Number
RW
Indicates the number of the PCI bus to which the primary interface is connected.
The value is set in software during configuration.
Reset to 0
07-0067
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