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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 36/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 41 of 82
March 20, 2007 – Revision 1.01
4.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI
Local Bus Specification, Revision 2.2, provides the following alternative methods for synchronizing
data and interrupts:
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device before
accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are forwarded.
The bridge does not have a hardware mechanism to guarantee data synchronization for posted write
transactions. Therefore, all posted write transactions must be followed by a read operation, either from
the device to the location just written (or some other location along the same path), or from the device
driver to one of the device registers.
5
ERROR HANDLING
The bridge checks, forwards, and generates parity on both the primary and secondary interfaces. To
maintain transparency, the bridge always tries to forward the existing parity condition on one bus to the
other bus, along with address and data. The bridge always attempts to be transparent when reporting
errors, but this is not always possible, given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, the bridge implements the following:
PERR# and SERR# signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR# event disable register
This chapter provides detailed information about how the bridge handles errors. It also describes error
status reporting and error operation disabling.
5.1
ADDRESS PARITY ERRORS
The bridge checks address parity for all transactions on both buses, for all address and all bus
commands. When the bridge detects an address parity error on the primary interface, the following
events occur:
If the parity error response bit is set in the command register, the bridge does not claim the
transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If
parity error response bit is not set, the bridge proceeds normally and accepts the transaction if it
is directed to or across the bridge.
The bridge sets the detected parity error bit in the status register.
The bridge asserts P_SERR# and sets signaled system error bit in the status register, if both the
following conditions are met:
The SERR# enable bit is set in the command register.
The parity error response bit is set in the command register.
07-0067
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8148ANBE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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