參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 8/82頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 16 of 82
March 20, 2007 – Revision 1.01
Pin Number
Name
Type
Pin Number
Name
Type
115
P_CLKRUN#
TS
116
P_RST#
I
117
P_CLK
I
118
P_GNT#
I
119
P_REQ#
TS
120
VDD
P
121
P_AD[31]
TS
122
P_AD[30]
TS
123
P_AD[29]
TS
124
P_AD[28]
TS
125
P_AD[27]
TS
126
P_AD[26]
TS
127
P_AD[25]
TS
128
VSS
P
2
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across the bridge, and
transaction termination. The bridge has two 128-byte FIFO’s for buffering of upstream and
downstream transactions. These hold addresses, data, commands, and byte enables that are used for
write transactions. The bridge also has an additional four 128-byte FIFO’s that hold addresses, data,
commands, and byte enables for read transactions.
2.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by the bridge. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support for
each transaction when the bridge initiates transactions as a master, on the primary (P) and secondary (S)
buses, and when the bridge responds to transactions as a target, on the primary (P) and secondary (S)
buses.
Table 2-1. PCI Transactions
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
0001
Special Cycle
Y
N
0010
I/O Read
Y
0011
I/O Write
Y
0100
Reserved
N
0101
Reserved
N
0110
Memory Read
Y
0111
Memory Write
Y
1000
Reserved
N
1001
Reserved
N
1010
Configuration Read
N
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
1101
Dual Address Cycle
Y
1110
Memory Read Line
Y
1111
Memory Write and Invalidate
Y
As indicated in Table 2-1, the following PCI commands are not supported by the bridge:
The bridge never initiates a PCI transaction with a reserved command code and, as a target, the
bridge ignores reserved command codes.
The bridge does not generate interrupt acknowledge transactions. The bridge ignores interrupt
acknowledge transactions as a target.
07-0067
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