參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 5/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 13 of 82
March 20, 2007 – Revision 1.01
Name
Pin Number
Type
Description
S_PAR
67
TS
Secondary Parity: Parity is even across S_AD[31:0],
S_CBE#[3:0], and S_PAR (i.e. an even number of 1’s). S_PAR
is an input and is valid and stable one cycle after the address
phase (indicated by assertion of S_FRAME#) for address parity.
For write data phases, S_PAR is an input and is valid one clock
after S_IRDY# is asserted. For read data phase, S_PAR is an
output and is valid one clock after S_TRDY# is asserted. Signal
S_PAR is tri-stated one cycle after the S_AD lines are tri-stated.
During bus idle, PI7C8140A drives S_PAR to a valid logic level
when the internal grant is asserted.
S_FRAME#
74
STS
Secondary FRAME (Active LOW): Driven by the initiator of a
transaction to indicate the beginning and duration of an access.
The de-assertion of S_FRAME# indicates the final data phase
requested by the initiator. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
S_IRDY#
73
STS
Secondary IRDY (Active LOW): Driven by the initiator of a
transaction to indicate its ability to complete current data phase
on the secondary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
S_TRDY#
72
STS
Secondary TRDY (Active LOW): Driven by the target of a
transaction to indicate its ability to complete current data phase
on the secondary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
S_DEVSEL#
71
STS
Secondary Device Select (Active LOW): Asserted by the target
indicating that the device is accepting the transaction. As a
master, PI7C8140A waits for the assertion of this signal within 5
cycles of S_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a de-asserted state
for one cycle.
S_STOP#
70
STS
Secondary STOP (Active LOW): Asserted by the target
indicating that the target is requesting the initiator to stop the
current transaction. Before tri-stated, it is driven to a de-asserted
state for one cycle.
S_PERR#
69
STS
Secondary Parity Error (Active LOW): Asserted when a data
parity error is detected for data received on the secondary
interface. Before being tri-stated, it is driven to a de-asserted
state for one cycle.
S_SERR#
68
I
Secondary System Error (Active LOW): Can be driven LOW
by any device to indicate a system error condition.
S_REQ#[3:0]
99, 98, 97, 96
I
Secondary Request (Active LOW): This is asserted by an
external device to indicate that it wants to start a transaction on
the secondary bus. The input is externally pulled up through a
resistor to VDD.
S_GNT#[3:0]
104, 103, 101, 100
TS
Secondary Grant (Active LOW): PI7C8140A asserts these
pins to allow external masters to access the secondary bus.
PI7C8140A de-asserts these pins for at least 2 PCI clock cycles
before asserting it again. During idle and S_GNT# deasserted,
PI7C8140A will drive S_AD, S_CBE, and S_PAR.
S_RST#
105
O
Secondary RESET (Active LOW): Asserted when any of the
following conditions are met:
1.
Signal P_RESET# is asserted.
2.
Secondary reset bit in bridge control register in
configuration space is set.
When asserted, all control signals are tri-stated and zeroes are
driven on S_AD, S_CBE, and S_PAR.
07-0067
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