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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 71/82頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 73 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
5:4
Clock 2 disable
RW
S_CLKOUT[2] (slot 2) Enable
00: enable S_CLKOUT[2]
01: enable S_CLKOUT[2]
10: enable S_CLKOUT[2]
11: disable S_CLKOUT[2] and driven LOW
Reset to 00
7:6
Clock 3 disable
RW
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven LOW
Reset to 00
8
Reserved
RO
Reserved. Reset to 0
13:9
Reserved
RO
Reserved. Reset to 1Fh
15:14
Reserved
RO
Reserved. Reset to 00
13.2.37 P_SERR# STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
16
Address Parity
Error
RWC
1: Signal P_SERR# was asserted because an address parity error was detected on
P or S bus.
Reset to 0
17
Posted Write
Data Parity
Error
RWC
1: Signal P_SERR# was asserted because a posted write data parity error was
detected on the target bus.
Reset to 0
18
Posted Write
Non-delivery
RWC
1: Signal P_SERR# was asserted because the bridge was unable to deliver post
memory write data to the target after 2
24 attempts.
Reset to 0
19
Target Abort
during Posted
Write
RWC
1: Signal P_SERR# was asserted because the bridge received a target abort when
delivering post memory write data.
Reset to 0.
20
Master Abort
during Posted
Write
RWC
1: Signal P_SERR# was asserted because the bridge received a master abort when
attempting to deliver post memory write data
Reset to 0.
21
Delayed Write
Non-delivery
RWC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 2
24 attempts.
Reset to 0
22
Delayed Read –
No Data from
Target
RWC
1: Signal P_SERR# was asserted because the bridge was unable to read any data
from the target after 2
24 attempts.
Reset to 0.
23
Delayed
Transaction
Master Timeout
RWC
1: Signal P_SERR# was asserted because a master did not repeat a read or write
transaction before master timeout.
Reset to 0.
07-0067
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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