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參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 37/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 42 of 82
March 20, 2007 – Revision 1.01
When the bridge detects an address parity error on the secondary interface, the following events occur:
If the parity error response bit is set in the bridge control register, the bridge does not claim the
transaction with S_DEVSEL#; this may allow the transaction to terminate in a master abort. If
parity error response bit is not set, the bridge proceeds normally and accepts transaction if it is
directed to or across the bridge.
The bridge sets the detected parity error bit in the secondary status register.
The bridge asserts P_SERR# and sets signaled system error bit in status register, if both of the
following conditions are met:
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
5.2
DATA PARITY ERRORS
When forwarding transactions, the bridge attempts to pass the data parity condition from one interface
to the other unchanged, whenever possible, to allow the master and target devices to handle the error
condition.
The following sections describe, for each type of transaction, the sequence of events that occurs when a
parity error is detected and the way in which the parity condition is forwarded across the bridge.
5.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION
SPACE
When the bridge detects a data parity error during a Type 0 configuration write transaction to the bridge
configuration space, the following events occur:
If the parity error response bit is set in the command register, the bridge asserts P_TRDY# and writes
the data to the configuration register. The bridge also asserts P_PERR#. If the parity error response bit
is not set, the bridge does not assert P_PERR#.
The bridge sets the detected parity error bit in the status register, regardless of the state of the parity
error response bit.
5.2.2
READ TRANSACTIONS
When the bridge detects a parity error during a read transaction, the target drives data and data parity,
and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when the
bridge detects a read data parity error on the secondary bus, the following events occur:
Bridge asserts S_PERR# two cycles following the data transfer, if the secondary interface parity
error response bit is set in the bridge control register.
Bridge sets the detected parity error bit in the secondary status register.
Bridge sets the data parity detected bit in the secondary status register, if the secondary interface
parity error response bit is set in the bridge control register.
Bridge forwards the bad parity with the data back to the initiator on the primary bus. If the data
with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is
discarded and the data with bad parity is not returned to the initiator.
07-0067
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| PI7C8148ANJE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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