參數(shù)資料
型號(hào): PI7C8140AMAE
廠商: Pericom
文件頁數(shù): 6/82頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝: 39
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 14 of 82
March 20, 2007 – Revision 1.01
1.2.3
CLOCK SIGNALS
Name
Pin Number
Type
Description
P_CLK
117
I
Primary Clock Input: Provides timing for all transactions on
the primary interface.
S_CLKOUT[3:0]
110, 109, 108, 107
O
Secondary Clock Output: Provides secondary clocks phase
synchronous with the P_CLK.
P_CLKRUN#
115
TS
Primary Clock Run: Allows main system to stop the primary
clock based on the specifications in the PCI Mobile Design
Guide, Revision 1.0. If unused, this pin should be tied to ground
to signify that P_CLK is always running.
S_CLKRUN#
112
TS
Secondary Clock Run: Allows main system to slow down or
stop the secondary clock and is controlled by the primary or
bit[4] offset 6Fh. If the secondary devices do not support
CLKRUN, this pin should be pulled LOW by a 300 ohm resistor.
1.2.4
MISCELLANEOUS SIGNALS
Name
Pin Number
Type
Description
ENUM#
113
O
Hot Swap Status Indicator: The output of ENUM# indicates to
the system that an insertion has occurred or that an extraction is
about to occur.
LOO
114
I/O
Hot Swap LED: The output of this pin lights an LED to indicate
insertion or removal ready status. This pin may also be used as a
input or detect pin. Every 500us, the pin tri-states for 8 primary
PCI clock cycles to sample the status.
SCAN_TM#
65
I
Full-Scan Test Mode Enable: For normal operation, pull
SCAN_TM# to HIGH. Manufacturing test pin.
SCAN_EN
106
I/O
Full-Scan Enable Control: For normal operation, SCAN_TM#
should be pulled HIGH and SCAN_EN becomes an output with
logic 0. Manufacturing test pin.
1.2.5
POWER AND GROUND
Name
Pin Number
Type
Description
VDD
1, 20, 39, 58, 84, 102,
120
P
Power: 3.3V power
VSS
11, 29, 38, 49, 64, 75,
93, 111, 128
P
Ground
07-0067
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