參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 3/82頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 11 of 82
March 20, 2007 – Revision 1.01
1
SIGNAL DEFINITIONS
1.1
SIGNAL TYPES
SIGNAL TYPE
DESCRIPTION
I
Input only
O
Output only
P
Power
TS
Tri-state bi-directional
STS
Sustained tri-state. Active LOW signal must be pulled HIGH for 1 cycle
when deasserting.
OD
Open Drain
1.2
SIGNALS
Signals that end with “#” are active LOW.
1.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
Pin Number
Type
Description
P_AD[31:0]
121, 122, 123, 124,
125, 126, 127, 2, 5, 6,
7, 8, 9, 10, 12, 13, 25,
26, 27, 28, 30, 31, 32,
33, 35, 36, 37, 40, 41,
42, 43, 44
TS
Primary Address / Data: Multiplexed address and data bus.
Address is indicated by P_FRAME# assertion. Write data is
stable and valid when P_IRDY# is asserted and read data is
stable and valid when P_TRDY# is asserted. Data is transferred
on rising clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C8140A drives P_AD to a valid
logic level when P_GNT# is asserted.
P_CBE#[3:0]
3, 14, 24, 34
TS
Primary Command/Byte Enables: Multiplexed command field
and byte enable field. During address phase, the initiator drives
the transaction type on these pins. After that, the initiator drives
the byte enables during data phases. During bus idle, PI7C8140A
drives P_CBE#[3:0] to a valid logic level when P_GNT# is
asserted.
P_PAR
23
TS
Primary Parity. Parity is even across P_AD[31:0],
P_CBE#[3:0], and P_PAR (i.e. an even number of 1’s). P_PAR
is an input and is valid and stable one cycle after the address
phase (indicated by assertion of P_FRAME#) for address parity.
For write data phases, P_PAR is an input and is valid one clock
after P_IRDY# is asserted. For read data phase, P_PAR is an
output and is valid one clock after P_TRDY# is asserted. Signal
P_PAR is tri-stated one cycle after the P_AD lines are tri-stated.
During bus idle, PI7C8140A drives P_PAR to a valid logic level
when P_GNT# is asserted.
P_FRAME#
15
STS
Primary FRAME (Active LOW). Driven by the initiator of a
transaction to indicate the beginning and duration of an access.
The de-assertion of P_FRAME# indicates the final data phase
requested by the initiator. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
P_IRDY#
16
STS
Primary IRDY (Active LOW). Driven by the initiator of a
transaction to indicate its ability to complete current data phase
on the primary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
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