參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 62/82頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 65 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
15:4
Memory Base
Address [15:4]
RW
Defines the bottom address of an address range for the bridge to determine when
to forward memory transactions from one interface to the other. The upper 12
bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be 0.
Reset to 0
13.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
Bit
Function
Type
Description
19:16
Reserved
RO
Reset to 0
31:20
Memory Limit
Address [31:20]
RW
Defines the top address of an address range for the bridge to determine when to
forward memory transactions from one interface to the other. The upper 12 bits
correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
13.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
Bit
Function
Type
Description
3:0
64-bit
addressing
RO
Indicates 64-bit addressing
0001: 64-bit addressing
Reset to 1
15:4
Prefetchable
Memory Base
Address [31:20]
RW
Defines the bottom address of an address range for the bridge to determine when
to forward memory read and write transactions from one interface to the other.
The upper 12 bits correspond to address bits [31:20] and are writable. The lower
20 bits are assumed to be 0. The memory base register upper 32 bits contains the
upper half of the base address.
13.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
Bit
Function
Type
Description
19:16
64-bit
addressing
RO
Indicates 64-bit addressing
0001: 64-bit addressing
Reset to 1
31:20
Prefetchable
Memory Limit
Address [31:20]
RW
Defines the top address of an address range for the bridge to determine when to
forward memory read and write transactions from one interface to the other. The
upper 12 bits correspond to address bits [31:20] and are writable. The lower 20
bits are assumed to be FFFFFh. The memory limit upper 32 bits register contains
the upper half of the limit address.
13.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER
– OFFSET 28h
Bit
Function
Type
Description
31:0
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
RW
Defines the upper 32-bits of a 64-bit bottom address of an address range for the
bridge to determine when to forward memory read and write transactions from
one interface to the other.
Reset to 0
07-0067
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