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參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 30/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 36 of 82
March 20, 2007 – Revision 1.01
on the secondary interface that fall into this address range. Any transactions that fall outside this address
range are ignored on the primary interface and are forwarded upstream from the secondary interface
(provided that they do not fall into the prefetchable memory range or are not forwarded downstream by
the VGA mechanism).
The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture
Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-
mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O
address range is 4GB.
The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address
register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset
22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The
low 4 bits are hardwired to 0. The lowest 20 bits of the memory-mapped I/O base address are assumed
to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the
memory-mapped I/O limit address are assumed to be FFFFFh, which results in an alignment to the top
of a 1MB block.
Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state
of the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these
registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers
with their appropriate values before setting either the memory enable bit or the master enable bit in the
command register in configuration space. To turn off the memory-mapped I/O address range, write the
memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O
limit address register.
3.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
Locations accessed in the prefetchable memory address range must have true memory-like behavior and
must not exhibit side effects when read. This means that extra reads to a prefetchable memory location
must have no side effects. The bridge prefetches for all types of memory read commands in this address
space.
The prefetchable memory base address and prefetchable memory limit address registers define an
address range that the bridge uses to determine when to forward memory commands. The bridge
forwards a memory transaction from the primary to the secondary interface if the transaction address
falls within the prefetchable memory address range. The bridge ignores memory transactions initiated
on the secondary interface that fall into this address range. The bridge does not respond to any
transactions that fall outside this address range on the primary interface and forwards those transactions
upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O
range or are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional registers to define
the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits
register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a
single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address
transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is
compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory
limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must
be 0 to pass any single address cycle transactions downstream.
07-0067
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