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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 4/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 12 of 82
March 20, 2007 – Revision 1.01
Name
Pin Number
Type
Description
P_TRDY#
17
STS
Primary TRDY (Active LOW). Driven by the target of a
transaction to indicate its ability to complete current data phase
on the primary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
P_DEVSEL#
18
STS
Primary Device Select (Active LOW). Asserted by the target
indicating that the device is accepting the transaction. As a
master, PI7C8140A waits for the assertion of this signal within 5
cycles of P_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a de-asserted state
for one cycle.
P_STOP#
19
I
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to stop the
current transaction. Before tri-stated, it is driven to a de-asserted
state for one cycle.
P_IDSEL
4
I
Primary ID Select. Used as a chip select line for Type 0
configuration access to PI7C8140A configuration space.
P_PERR#
21
STS
Primary Parity Error (Active LOW). Asserted when a data
parity error is detected for data received on the primary interface.
Before being tri-stated, it is driven to a de-asserted state for one
cycle.
P_SERR#
22
OD
Primary System Error (Active LOW). Can be driven LOW by
any device to indicate a system error condition. PI7C8140A
drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for proper
operation.
P_REQ#
119
TS
Primary Request (Active LOW): This is asserted by
PI7C8140A to indicate that it wants to start a transaction on the
primary bus. PI7C8140A de-asserts this pin for at least 2 PCI
clock cycles before asserting it again.
P_GNT#
118
I
Primary Grant (Active LOW): When asserted, PI7C8140A can
access the primary bus. During idle and P_GNT# asserted,
PI7C8140A will drive P_AD, P_CBE, and P_PAR to valid logic
levels.
P_RST#
116
I
Primary RESET (Active LOW): When P_RST# is active, all
PCI signals should be asynchronously tri-stated.
1.2.2
SECONDARY BUS INTERFACE SIGNALS
Name
Pin Number
Type
Description
S_AD[31:0]
95, 94, 92, 91, 90, 89,
88, 87, 85, 83, 82, 81,
80, 79, 78, 77, 63, 62,
61, 60, 59, 57, 56, 55,
53, 52, 51, 50, 48, 47,
46, 45
TS
Secondary Address/Data: Multiplexed address and data bus.
Address is indicated by S_FRAME# assertion. Write data is
stable and valid when S_IRDY# is asserted and read data is
stable and valid when S_TRDY# is asserted. Data is transferred
on rising clock edges when both S_IRDY# and S_TRDY# are
asserted. During bus idle, PI7C8140A drives S_AD to a valid
logic level when S_GNT# is asserted respectively.
S_CBE#[3:0]
86, 76, 66, 54
TS
Secondary Command/Byte Enables: Multiplexed command
field and byte enable field. During address phase, the initiator
drives the transaction type on these pins. The initiator then
drives the byte enables during data phases. During bus idle,
PI7C8140A drives S_CBE#[3:0] to a valid logic level when the
internal grant is asserted.
07-0067
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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