參數(shù)資料
型號: PI7C8140AMAE
廠商: Pericom
文件頁數(shù): 68/82頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標準包裝: 39
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應商設備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 70 of 82
March 20, 2007 – Revision 1.01
13.2.32 ARBITER CONTROL REGISTER – OFFSET 44h
Bit
Function
Type
Description
19:16
Arbiter Control
RW
Each bit controls whether a secondary bus master is assigned to the high priority
group or the low priority group.
Bits [19:16] correspond to request inputs S_REQ#[3:0]
0: low priority
1: high priority
Reset to 0
24:20
Reserved
RO
Reserved. Returns 0 when read. Reset to 0.
25
Priority of
Secondary
Interface
RW
Controls whether the secondary interface of the bridge is in the high priority
group or the low priority group.
0: low priority
1: high priority
Reset to 1
31:26
Reserved
RO
Reserved. Returns 0 when read. Reset to 0.
13.2.33 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
0
Memory Read
Flow Through
Enable
RW
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
1
Park
RW
Controls bus arbiter’s park function
0: Park to last master
1: Park to the bridge – secondary port
Reset to 0
2
Downstream
Dynamic
Prefetching
Control
RW
Controls the downstream (P to S) memory read line and memory read multiple
prefetching dynamic control
0: Enable the downstream memory read line and memory read multiple
prefetching dynamic control
1: Disable the downstream memory read line and memory read multiple
prefetching dynamic control
Reset to 0
3
Upstream
Dynamic
Prefetching
Control
RW
Controls the upstream (S to P) memory read line and memory read multiple
prefetching dynamic control
0: Enable the upstream memory read line and memory read multiple prefetching
dynamic control
1: Disable the upstream memory read line and memory read multiple prefetching
dynamic control
Reset to 0
07-0067
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