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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 29/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 35 of 82
March 20, 2007 – Revision 1.01
are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as
defined by the address range defined by the I/O base and limit registers.
Accordingly, if the ISA enable bit is set, the bridge forwards upstream those I/O transactions addressing
the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit
in the command configuration register must also be set to enable upstream forwarding. All other I/O
transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O
address range.
When the ISA enable bit is set, devices downstream of the bridge can have I/O space mapped into the
first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the
64KB boundary.
3.3
MEMORY ADDRESS DECODING
The bridge has three mechanisms for defining memory address ranges for forwarding of memory
transactions:
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
This section describes the first two mechanisms. Section 3.4.1 describes VGA mode. To enable
downstream forwarding of memory transactions, the memory enable bit must be set in the command
register in configuration space. To enable upstream forwarding of memory transactions, the master-
enable bit must be set in the command register. The master-enable bit also allows upstream forwarding
of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a configuration write
operation on the primary bus at the same time that memory transactions are ongoing on the secondary
bus, response to the secondary bus memory transactions is not predictable. Configure the memory-
mapped I/O base and limit address registers, prefetchable memory base and limit address registers,
and VGA mode bit before setting the memory enable and master enable bits, and change them
3.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot
automatically be pre-fetched but that can be conditionally pre-fetched based on command type should
be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this
space may have non-memory-like behavior. The bridge prefetches in this space only if the memory
read line or memory read multiple commands are used; transactions using the memory read command
are limited to a single data transfer.
The memory-mapped I/O base address and memory-mapped I/O limit address registers define an
address range that the bridge uses to determine when to forward memory commands. The bridge
forwards a memory transaction from the primary to the secondary interface if the transaction address
falls within the memory-mapped I/O address range. The bridge ignores memory transactions initiated
07-0067
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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