參數(shù)資料
型號： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 47/82頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 51 of 82
March 20, 2007 – Revision 1.01
S_IRDY# is asserted, the arbiter can be de-asserted one grant and asserted another grant during the
same PCI clock cycle.
6.2.1
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit [31:28]).
Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0) clocks. If the current
master occupies the bus and other masters are waiting, the current master will be preempted by
removing its grant (GNT#) after the next master waits for the time-to-preempt.
6.2.2
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the bus is
idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning
another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and
the device’s request is not asserted. The AD and CBE signals should be driven first, with the PAR
signal driven one cycle later.
The bridge parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the
primary PCI bus is idle. When P_GNT# is de-asserted, the bridge 3-states the P_AD, P_CBE, and
P_PAR signals on the next PCI clock cycle. If the bridge is parking the primary PCI bus and wants to
initiate a transaction on that bus, then the bridge can start the transaction on the next PCI clock cycle by
asserting P_FRAME# if P_GNT# is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master
that used the PCI bus. That is, the bridge keeps the secondary bus grant asserted to a particular master
until a new secondary bus request comes along. After reset, the bridge parks the secondary bus at itself
until transactions start occurring on the secondary bus. Offset 48h, bit [1], can be set to 1 to park the
secondary bus at PI7C8140A. By default, offset 48h, bit [1], is set to 0.
7
CLOCKS
This chapter provides information about the clocks.
7.1
PRIMARY CLOCK INPUTS
The bridge implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the
secondary clock. In synchronous mode, the secondary clock is derived internally from the primary
clock, P_CLK. The bridge operates at a maximum frequency of 66 MHz.
07-0067
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