參數(shù)資料
型號(hào): PI7C8140AMAE
廠商: Pericom
文件頁數(shù): 75/82頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝: 39
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 77 of 82
March 20, 2007 – Revision 1.01
13.2.43 POWER MANAGEMENT DATA REGISTER – OFFSET 84h
Bit
Function
Type
Description
1:0
Power State
RW
Indicates the current power state of the bridge. If an unimplemented power state
is written to this register, the bridge completes the write transaction, ignores the
write data, and does not change the value of the field. Writing a value of D0
when the previous state was D3 cause a chip reset without asserting S_RESET#
00: D0 state
01: D1 state
10: D2 state
11: D3 state
Reset to 0
7:2
Reserved
RO
Read as 0
8
PME# Enable
RO
Read as 0 as the bridge does not support the PME# pin.
12:9
Data Select
RO
Read as 0 as the data register is not implemented.
14:13
Data Scale
RO
Read as 0 as the data register is not implemented.
15
PME status
RO
Read as 0 as the PME# pin is not implemented.
13.2.44 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h
Bit
Function
Type
Description
15:0
Primary
Timeout
RW
Primary timeout occurs after 2
15 PCI clocks.
Reset to 8000h.
13.2.45 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h
Bit
Function
Type
Description
31:16
Secondary
Timeout
RW
Secondary timeout occurs after 2
15 PCI clocks.
Reset to 8000h.
13.2.46 CAPABILITY ID REGISTER – OFFSET 90h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities ID
RO
Read as 06h to indicate that these are power management enhanced capability
registers.
13.2.47 NEXT ITEM POINTER REGISTER – OFFSET 90h
Bit
Function
Type
Description
15:8
Next Item
Pointer
RO
Read as 00h. No other ECP registers.
07-0067
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