參數(shù)資料
型號(hào): PI7C8140AMAE
廠商: Pericom
文件頁(yè)數(shù): 64/82頁(yè)
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝: 39
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-QFP(14x20)
包裝: 管件
安裝類型: 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 67 of 82
March 20, 2007 – Revision 1.01
13.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
16
Parity Error
Response
RW
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary interface
Reset to 0
17
S_SERR#
enable
RW
0: disable the forwarding of S_SERR# to primary interface
1: enable the forwarding of S_SERR# to primary interface
Reset to 0
18
ISA enable
RW
Modifies the bridge’s response to ISA I/O addresses, applying only to those
addresses falling within the I/O base and limit address registers and within the
first 64KB of PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and I/O limit
registers
1: blocks forwarding of ISA I/O addresses in the range defined by the I/O base
and I/O limit registers that are in the first 64KB of I/O space that address the last
768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream
if the address falls within the last 768 bytes in each 1KB block
Reset to 0
19
VGA enable
RW
0: does not forward VGA compatible memory and I/O addresses from primary to
secondary
1: forward VGA compatible memory and I/O addresses from primary to
secondary regardless of other settings
Reset to 0
20
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
21
Master Abort
Mode
RW
0: does not report master aborts (returns FFFF_FFFFh on reads and discards data
on writes)
1: reports master aborts by signaling target abort if possible or by the assertion of
P_SERR# if enabled
Reset to 0
22
Secondary
Interface Reset
RW
0: does not force the assertion of S_RESET# pin
1: forces the assertion of S_RESET#
Reset to 0
23
Fast Back-to-
Back Enable
RW
Controls bridge’s ability to generate fast back-to-back transactions to different
devices on the secondary interface.
0: does not generate fast back-to-back transactions on the secondary
1: enables fast back-to-back transaction generation on the secondary
Reset to 0
07-0067
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