參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 24/82頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 30 of 82
March 20, 2007 – Revision 1.01
Bridge completes at least one data transfer.
Bridge receives a master abort.
Bridge receives a target abort.
The bridge makes 2
24 (default) or 232 (maximum) write attempts resulting in a response of target retry.
Table 2-7. Delayed Write Target Termination Response
Target Termination
Response
Normal
Returning disconnect to initiator with first data transfer only if multiple data phases requested.
Target Retry
Returning target retry to initiator. Continue write attempts to target
Target Disconnect
Returning disconnect to initiator with first data transfer only if multiple data phases requested.
Target Abort
Returning target abort to initiator. Set received target abort bit in target interface status register.
Set signaled target abort bit in initiator interface status register.
After the bridge makes 2
24 (default) attempts of the same delayed write trans-action on the target bus,
the bridge asserts P_SERR# if the SERR# enable bit (bit 8 of command register for the secondary bus)
is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of
P_SERR# event disable register (offset 64h). The bridge will report system error. See Section 5.4 for a
description of system error conditions.
2.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE
When the bridge initiates a posted write transaction, the target termination cannot be passed back to the
initiator. Table 2-8 shows the response to each type of target termination that occurs during a posted
write transaction.
Table 2-8. Response to Posted Write Target Termination
Target Termination
Repsonse
Normal
No additional action.
Target Retry
Repeating write transaction to target.
Target Disconnect
Initiate write transaction for delivering remaining posted write data.
Target Abort
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data associated with that
transaction remains in the write buffers, the bridge initiates another write transaction to attempt to
deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for
the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a
subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If
the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write
data to the target is performed before a target disconnect is received, the bridge will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line will be
transferred in the subsequent write transaction attempt.
After the bridge makes 2
24 (default) write transaction attempts and fails to deliver all posted write data
associated with that transaction, the bridge asserts P_SERR# if the primary SERR# enable bit is set (bit
8 of command register for secondary bus) and posted-write-non-delivery bit is not set. The posted-
write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). The bridge will report
system error. See Section 5.4 for a discussion of system error conditions.
07-0067
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