參數(shù)資料
型號： PI7C8140AMAE
廠商： Pericom
文件頁數(shù)： 43/82頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 48 of 82
March 20, 2007 – Revision 1.01
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
The bridge is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
The bridge detects a data parity error on the primary bus or detects S_PERR# asserted during the
completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 5-5. Assertion of P_PERR#
P_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0 (asserted)
Read
Upstream
Primary
1 / x
1
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
1 / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
1 / x
0
2
Delayed Write
Downstream
Secondary
1 / 1
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
The bridge is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
Bridge detects a data parity error on the secondary bus or detects P_PERR# asserted during the
completion phase of an upstream delayed write transaction on the target (primary) bus.
Table 5-6. Assertion of S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
0
2
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions:
07-0067
相關(guān)PDF資料
PDF描述
PI7C8150ANDE IC PCI-PCI BRIDGE 2PORT 256-PBGA
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
PI7C8154ANAE IC PCI-PCI BRIDGE ASYNC 304-PBGA
PI7C8154BNAIE IC PCI-PCI BRIDGE ASYNC 304-PBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8148A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
PI7C8148AEVB 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8148ANBE 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8148ANJ 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
PI7C8148ANJE 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*