- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8140AMAE (Pericom)IC PCI-PCI BRIDGE 2PORT 128-QFP PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 21/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 28 of 82
March 20, 2007 – Revision 1.01
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data
phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or
STOP# assertion from the target.
Master abort
A master abort occurs when no target response is detected. When the initiator does not detect a
DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates
the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME#
on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in
the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be
de-asserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted.
Target retry
STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made. Indicates that no more data transfers will be made during this transaction.
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
2.8.1
MASTER TERMINATION INITIATED BY PI7C8140A
The bridge, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock
cycles of the bridge’s assertion of FRAME# on the target bus. As an initiator, the bridge terminates a
transaction when the following conditions are met:
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers to
the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master
latency timer expires and the bridge’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
If the bridge is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The address of
the transaction is updated to reflect the address of the current DWORD to be delivered.
07-0067
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150ANDE | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| PI7C8150BNDIE | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| PI7C8152BMAIE | IC PCI-PCI BRIDGE 2PORT 160-MQFP |
| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8148ANBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。