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| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 15/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 22 of 82
March 20, 2007 – Revision 1.01
2.6.4
READ PREFETCH ADDRESS BOUNDARIES
The bridge imposes internal read address boundaries on read pre-fetched data. When a read transaction
reaches one of these aligned address boundaries, the bridge stops pre-fetched data, unless the target
signals a target disconnect before the read pre-fetched boundary is reached. When the bridge finishes
transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless
the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-
fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME_L. Section 2.6.7 describes flow-through mode during
read operations.
Table 2-4 shows the read prefetch address boundaries for read transactions during non-flow-through
mode.
Table 2-4. Read Prefetch Address Boundaries
Type of Transaction
Address Space
Cache
Line
Size
(CLS)
Prefetch Aligned Address Boundary
Configuration Read
-
*
One DWORD (no prefetch)
I/O Read
-
*
One DWORD (no prefetch)
Memory Read
Non-Prefetchable
*
One DWORD (no prefetch)
Memory Read
Prefetchable
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read
Prefetchable
CLS = 1, 2, 4, 8, 16
Cache line address boundary
Memory Read Line
-
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read Line
-
CLS = 1, 2, 4, 8, 16
Cache line boundary
Memory Read Multiple
-
CLS = 0 or 16
32-DWORD aligned address boundary
Memory Read Multiple
-
CLS = 1, 2, 4, 8, 16
2X of cache line boundary
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5. Read Transaction Prefetching
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
2.6.5
DELAYED READ REQUESTS
The bridge treats all read transactions as delayed read transactions, which means that the read request
from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the
read data queue directed toward the initiator bus interface and is transferred to the initiator when the
initiator repeats the read transaction.
When the bridge accepts a delayed read request, it first samples the read address, read bus command,
and address parity. When IRDY# is asserted, the bridge then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. The bridge terminates the
transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is
07-0067
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| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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