參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 58/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 61 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
7
Wait Cycle
Control
RO
Read as 0 to indicate PI7C8140A does not perform address / data stepping.
Reset to 0
8
P_SERR#
enable
RW
0: disable the P_SERR# driver
1: enable the P_SERR# driver
Reset to 0
9
Fast Back-to-
Back Enable
RW
0: disable bridge’s ability to initiate fast back-to-back transactions on the primary
1: enable bridge’s ability to initiate fast back-to-back transactions on the primary
Reset to 0
15:10
Reserved
RO
Returns 000000 when read
13.2.4 PRIMARY STATUS REGISTER – OFFSET 04h
Bit
Function
Type
Description
19:16
Reserved
RO
Reset to 0000
20
Capabilities
List
RO
Set to 1 to enable support for the capability list (offset 34h is the pointer to the
data structure)
Reset to 1
21
66MHz
Capable
RO
Set to 1 to indicate the primary may be run at 66MHz operation
Reset to 1
22
Reserved
RO
Reset to 0
23
Fast Back-to-
Back Capable
RO
Set to 1 to enable decoding of fast back-to-back transactions on the primary
interface to different targets
Reset to 1
24
Data Parity
Error Detected
RWC
0: No parity error detected on the primary (bridge is the primary bus master)
1: Parity error detected on the primary (bridge is the primary bus master)
Reset to 0
26:25
DEVSEL#
timing
RO
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
27
Signaled Target
Abort
RWC
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
28
Received
Target Abort
RWC
Set to 1 (by a master device) whenever transactions are terminated with target
aborts
Reset to 0
29
Received
Master Abort
RWC
Set to 1 (by a master) when transactions are terminated with Master Abort
Reset to 0
30
Signaled
System Error
RWC
Set to 1 when P_SERR# is asserted
Reset to 0
31
Detected Parity
Error
RWC
Set to 1 when address or data parity error is detected on the primary interface
Reset to 0
07-0067
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