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| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 25/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 31 of 82
March 20, 2007 – Revision 1.01
2.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE
When the bridge initiates a delayed read transaction, the abnormal target responses can be passed back
to the initiator. Other target responses depend on how much data the initiator requests. Table 2-9 shows
the response to each type of target termination that occurs during a delayed read transaction.
The bridge repeats a delayed read transaction until one of the following conditions is met:
Bridge completes at least one data transfer.
Bridge receives a master abort.
Bridge receives a target abort.
The bridge makes 2
24 (default) read attempts resulting in a response of target retry.
Table 2-9. Response to Delayed Read Target Termination
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read from target. If
non-prefetchable, target disconnect on first data phase.
Target Retry
Re-initiate read transaction to target
Target Disconnect
If initiator requests more data than read from target, return target disconnect to initiator.
Target Abort
Return target abort to initiator. Set received target abort bit in the target interface status
register. Set signaled target abort bit in the initiator interface status register.
After the bridge makes 2
24(default) attempts of the same delayed read transaction on the target bus, the
bridge asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is
bit 5 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section
5.4 for a description of system error conditions.
2.8.4
TARGET TERMINATION INITIATED BY PI7C8140A
The bridge can return a target retry, target disconnect, or target abort to an initiator for reasons other
than detection of that condition at the target interface.
2.8.4.1 TARGET RETRY
The bridge returns a target retry to the initiator when it cannot accept write data or return read data as a
result of internal conditions. The bridge returns a target retry to an initiator when any of the following
conditions is met:
For delayed write transactions:
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target response has not yet
been received.
Target response has been received but has not progressed to the head of the return queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across the bridge, and the write transaction is not a locked
transaction.
The target bus is locked and the write transaction is a locked transaction.
07-0067
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相關(guān)代理商/技術(shù)參數(shù) |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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