參數(shù)資料
型號(hào)： PI7C8140AMAE
廠商： Pericom
文件頁(yè)數(shù)： 41/82頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 128-QFP
標(biāo)準(zhǔn)包裝： 39
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-QFP（14x20）
包裝： 管件
安裝類型： 表面貼裝
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 46 of 82
March 20, 2007 – Revision 1.01
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the secondary interface.
The parity error response bit is set in the command register of the primary interface.
Bridge has not detected the parity error on the secondary (initiator) bus, which the parity
error is not forwarded from the secondary bus to the primary bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that
the error occurred. Because the data has already been delivered with no errors, there is no other way to
signal this information back to the initiator. If the parity error has forwarded from the initiating bus to
the target bus, P_SERR# will not be asserted.
5.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of the bridge to data parity errors are presented according to the
type of transaction in progress. This section organizes the responses of the bridge to data parity errors
according to the status bits that the bridge sets and the signals that it asserts. Table 5-1 shows setting
the detected parity error bit in the status register, corresponding to the primary interface. This bit is set
when the bridge detects a parity error on the primary interface.
Table 5-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 5-2 shows setting the detected parity error bit in the secondary status register, corresponding to
the secondary interface. This bit is set when the bridge detects a parity error on the secondary interface.
Table 5-2. Setting Secondary Interface Detected Parity Error Bit
Secondary
Detected
Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
07-0067
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