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參數(shù)資料
| 型號(hào)： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 53/82頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 57 of 82
March 20, 2007 – Revision 1.01
Initiator
Target
Response
Master on Primary
Target on Secondary
Bridge asserts P_DEVSEL#, terminates the cycle
normally if it is able to be posted, otherwise return
with a retry. It then passes the cycle to the appropriate
port. When the cycle is complete on the target port, it
will wait for the initiator to repeat the same cycle and
end with normal termination.
Master on Primary
Target not on Primary nor
Secondary Port
Bridge does not respond and the cycle will terminate
as master abort.
Master on Secondary
Target on the same
Secondary Port
Bridge does not respond.
Master on Secondary
Target on Primary or the
other Secondary Port
Bridge asserts S_DEVSEL#, terminates the cycle
normally if it is able to be posted, otherwise returns
with a retry. It then passes the cycle to the appropriate
port. When cycle is complete on the target port, it will
wait for the initiator to repeat the same cycle and end
with normal termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
Bridge does not respond.
12.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
12.2.1 MASTER ABORT
Master abort indicates that when the bridge acts as a master and receives no response (i.e., no target
asserts DEVSEL# or S_DEVSEL#) from a target, the bridge de-asserts FRAME# and then deasserts
IRDY#.
12.2.2 PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, and S_PAR
signals. Parity should be even (i.e. an even number of‘1’s) across AD, CBE, and PAR. Parity
information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be
generated using the initiators CBE signals combined with the read data. Again, the PAR signal
corresponds to read data from the previous data phase cycle.
12.2.3 REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal
by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can
only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity
error should be reported by asserting the P_PERR_L signal two cycles after the data phase and should
remain asserted for one cycle when bit 6 in the Command register is set to a 1. The target reports any
type of data parity errors during write cycles, while the master reports data parity errors during read
cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus
(P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge
07-0067
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