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參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 48/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標準包裝： | 39 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 52 of 82
March 20, 2007 – Revision 1.01
7.2
SECONDARY CLOCK OUTPUTS
The bridge has 4 secondary clock outputs, S_CLKOUT[3:0] that can be used as clock inputs for up to
four external secondary bus devices. The S_CLKOUT[3:0] outputs are derived from P_CLK. The
secondary clock edges are delayed from P_CLK edges by a minimum of 0ns.
7.3
PCI CLOCKRUN
The bridge supports the PCI clock run protocol defined in the PCI Mobile Design Guide 1.0.
P_CLKRUN# is set HIGH when the system's central resource initiates to stop the primary clock
(P_CLK). The bridge will then signal that it allows the PCI clock to be stopped by keeping
P_CLKRUN# HIGH, or it will initiate P_CLK to remain running by driving P_CLKRUN# LOW for 2
clocks. After the 2 clocks have elapsed, the system’s central resource will keep P_CLKRUN# LOW.
There are 3 conditions where the bridge will keep the primary clock running:
Bit [26] offset 6Ch is set to 1
There is a pending transaction running through the bridge
A secondary device requires the clock
The secondary clock run protocol is enabled by bit [25] offset 6Ch. The primary is responsible for the
initiation of stopping or slowing down the secondary clock. The exception to this is if bit[28] offset
6Ch is set to 1. In this situation, the secondary clock will be stopped when the bus is idle and there are
no other cycles from the primary bus.
8
COMPACT PCI HOT SWAP
Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and removing PCI
boards form a Compact PCI system without powering down the system. The PI7C8140A is Hot Swap
Friendly silicon that supports all the cPCI Hot Swap Capable features and adds support for Software
Connection Control. Being Hot Swap Friendly, the bridge supports the following:
Compliance with PCI Specification 2.2
Tolerates VCC from Early Power
Asynchronous Reset
Tolerates Precharge Voltage
I/O Buffers Meet Modified V/I Requirements
Limited I/O Pin Leakage at Precharge Voltage
The bridge provides two pins to support hot swap: ENUM# and LOO. The ENUM# output indicates to
the system that an insertion event occurred or that an extraction is about to occur. The LOO output
lights an LED to signal insertion- and removal-ready status.
07-0067
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8148ANBE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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