- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1961 > PI7C8140AMAE (Pericom)IC PCI-PCI BRIDGE 2PORT 128-QFP PDF資料下載
參數(shù)資料
| 型號： | PI7C8140AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 50/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 128-QFP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-QFP（14x20） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 54 of 82
March 20, 2007 – Revision 1.01
10.2 SECONDARY INTERFACE RESET
The bridge is responsible for driving the secondary bus reset signals, S_RST#. The bridge asserts
S_RST# when any of the following conditions are met:
Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted and does
not de-assert until P_RST# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RST# remains asserted until a
configuration write operation clears the secondary reset bit.
S_RST# pin is asserted. When S_RST# is asserted, the bridge immediately 3-states all the secondary
PCI interface signals associated with the secondary port. The S_RST# in asserting and de-asserting
edges can be asynchronous to P_CLK.
When S_RST# is asserted, all secondary PCI interface control signals, including the secondary grant
outputs, are immediately 3-stated. Signals S1_AD, S1_CBE#[3:0], S_PAR are driven low for the
duration of S_RST# assertion. All posted write and delayed transaction data buffers are reset.
Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S_RST# is asserted by means of the secondary reset bit, the bridge remains accessible during
secondary interface reset and continues to respond to accesses to its configuration space from the
primary interface.
10.3 CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the bridge and the secondary
bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. S_RST#
is asserted and the secondary reset bit is automatically set. S_RST# remains asserted until a
configuration write operation clears the secondary reset bit and the serial clock mask has been shifted
in. Within 20 PCI clock cycles after completion of the configuration write operation, the bridge’s reset
bit automatically clears and the bridge is ready for configuration.
During reset, the bridge is inaccessible.
11
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
07-0067
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150ANDE | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| PI7C8150BNDIE | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| PI7C8152BMAIE | IC PCI-PCI BRIDGE 2PORT 160-MQFP |
| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148AEVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8148ANBE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148ANJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
| PI7C8148ANJE | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。