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6.9.2
DDR2 Memory Controller Peripheral Register Description(s)
6.9.3
DDR2 Memory Controller Electrical Data/Timing
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-27. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
0x7800 0000
0x7800 0004
0x7800 0008
0x7800 000C
0x7800 0010
0x7800 0014
0x7800 0018
0x7800 0020
0x7800 0024 - 0x7800 004C
0x7800 0050 - 0x7800 0078
0x7800 007C - 0x7800 00BC
0x7800 00C0 - 0x7800 00E0
0x7800 00E4
0x7800 00E8 - 0x7800 00FC
0x7800 0100 - 0x7FFF FFFF
ACRONYM
MIDR
DMCSTAT
SDCFG
SDRFC
SDTIM1
SDTIM2
-
BPRIO
-
-
-
-
DMCCTL
-
-
REGISTER NAME
DDR2 Memory Controller Module and Revision Register
DDR2 Memory Controller Status Register
DDR2 Memory Controller SDRAM Configuration Register
DDR2 Memory Controller SDRAM Refresh Control Register
DDR2 Memory Controller SDRAM Timing 1 Register
DDR2 Memory Controller SDRAM Timing 2 Register
Reserved
DDR2 Memory Controller Burst Priority Register
Reserved
Reserved
Reserved
Reserved
DDR2 Memory Controller Control Register
Reserved
Reserved
The
Implementing DDR2 PCB Layout on the TMS320DM647/DM648 DMSoC Application Report
(literature number
SPRAAK9
) specifies a complete DDR2 interface solution for the DM647/DM648 as well
as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to be
sure all DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is
supplied here for this interface.
NOTE
TI supports
only
designs that follow the board design guidelines outlined in the application
report, SPRAAA7, cited earlier.
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Peripheral Information and Electrical Specifications
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