參數(shù)資料
型號： TMX320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 6/166頁
文件大?。?/td> 1341K
代理商： TMX320DM647ZUT720
www.ti.com
P
2
Device Overview
2.1 Device Characteristics
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 2-1
, provides an overview of the TMS320DM647/TMS320DM648 DSPs. The tables show significant
features of the DM647/DM648 devices, including the capacity of on-chip RAM, the peripherals, the CPU
frequency, and the package type with pin count.
Table 2-1. Characteristics of the DM647/DM648 Processor
HARDWARE FEATURES
DDR2 memory controller (32-bit bus
width) [1.8 V I/O]
16-bit bus width
synchronous/asynchronous EMIF
[EMIFA]
EDMA3 (64 independent channels, 8
QDMA channels)
DM647
DM648
1
1
1
1
1
1
4 64-bit General Purpose
(each configurable as 1 64-bit
or
2
32-bit)
(with RTS and CTS flow control)
1 (Master/Slave)
1 (4-wire, 2 chip select)
1 (10 serailizers)
4 64-bit General Purpose
(each configurable as 1 64-bit
or
2
32-bit)
(with RTS and CTS flow control)
1 (Master/Slave)
1 (4-wire, 2 chip select)
1 (10 serailizers)
Timers
UART
I2C
SPI
McASP
3-port Ethernet Switch Subsystem
supporting 10/100/1000 Base-T
Management data input/output (MDIO)
VLYNQ
General-purpose input/output port
(GPIO)
HPI (16/32-bit)
PCI (32 bit) (33 MHz or 66 MHz)
VIC
Configurable video ports
Size (bytes)
Peripherals
Not all peripheral
pins are available
at the same time
(For more detail,
see
Section 3
.)
1 SGMII port available
2 SGMII ports available
1
1
Up to 32 pins
Up to 32 pins
1
1
1 (PCI33 or PCI66)
1
5
320KB RAM, 64KB ROM
32KB L1 program (L1P)/cache (Cache
up to 32KB)
32KB L1 data (L1D)/cache (Cache up
to 32KB)
256KB unified mapped RAM/Cache
(L2)
64KB Boot ROM
1 (PCI33 or PCI66)
1
5
576KB RAM, 64KB ROM
32KB L1 program (L1P)/cache (up to
32KB)
32KB L1 data (L1D)/cache (up to
32KB)
512 KB unified mapped RAM/Cache
(L2)
64KB Boot ROM
On-Chip Memory
Organization
Revision ID Register
(MM_REVID[15:0])
(address location 0x0181 2000)
MegaModule Rev
ID
0x0003
0x0003
CPU ID + CPU
Rev ID
Control Status Register (CSR.[31:16])
0x1000
0x1000
JTAGID register
(address location: 0x0204 9018)
MHz
ns
Core (V)
I/O (V)
CLKIN1 frequency multiplier
JTAG BSDL_ID
0x0B77 A02F
0x0B77 A02F
CPU Frequency
Cycle Time
720, 900
720, 900
1.39 ns (-720), 1.11 ns (-900)
1.2 V (-720, 900)
1.8 V, 3.3 V
x1 (Bypass), x15, x20, x25, x30, x32
529-Pin Flip Chip Plastic BGA (ZUT)
1.39 ns (-720), 1.11 ns (-900)
1.2 V (-720, 900)
1.8 V, 3.3 V
x1 (Bypass), x15, x20, x25, x30, x32
529-Pin Flip Chip Plastic BGA (ZUT)
Voltage
PLL Options
BGA Package
Device Overview
6
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