參數(shù)資料
型號: TMX320DM647ZUT720
廠商: Texas Instruments, Inc.
英文描述: Digital Media Processor
中文描述: 數(shù)字媒體處理器
文件頁數(shù): 133/166頁
文件大?。?/td> 1341K
代理商: TMX320DM647ZUT720
www.ti.com
P
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-55. PCI Back End Configuration Registers
DSP ACCESS
HEX ADDRESS RANGE
0x0204 8400 - 0x0204 840F
0x0204 8410
0x0204 8414
0x0204 8418 - 0x0204 841F
0x0204 8420
0x0204 8424
0x0204 8428 - 0x0204 842F
0x0204 8430
0x0204 8434
0x0204 8438
0x0204 843C - 0x0204 84FF
0x0204 8500
0x0204 8504
0x0204 8508
0x0204 850C
0x0204 8510
0x0204 8514
0x0204 8518
0x0204 851C
0x0204 8520
0x0204 8524
0x0204 8528 - 0x0204 852B
0x0204 852C
0x0204 8530
0x0204 8534
0x0204 8538 - 0x0204 853B
0x0204 853C
0x0204 8540 - 0x0204 857F
0x0204 8580
0x0204 8584 - 0x0204 85BF
0x0204 85C0
0x0204 85C4
0x0204 85C8
0x0204 85CC
0x0204 85D0
0x0204 85D4
0x0204 85D8 - 0x0204 85DF
0x0204 85E0
0x0204 85E4
0x0204 85E8
0x0204 85EC
0x0204 85F0
0x0204 85F4
0x0204 85F8 - 0x0204 86FF
0x0204 8700
0x0204 8704
ACRONYM
DSP ACCESS REGISTER NAME
-
Reserved
PCI Status Set Register
PCI Status Clear Register
Reserved
PCI Host Interrupt Enable Set Register
PCI Host Interrupt Enable Clear Register
Reserved
PCI Back End Application Interrupt Enable Set Register
PCI Back End Application Interrupt Enable Clear Register
PCI Back End Application Clock Management Register
Reserved
PCI Vendor ID/Device ID Mirror Register
PCI Command/Status Mirror Register
PCI Class Code/Revision ID Mirror Register
PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
PCI Base Address Mask Register 0
PCI Base Address Mask Register 1
PCI Base Address Mask Register 2
PCI Base Address Mask Register 3
PCI Base Address Mask Register 4
PCI Base Address Mask Register 5
Reserved
PCI Subsystem Vendor ID/Subsystem ID Mirror Register
Reserved
PCI Capabilities Pointer Mirror Register
Reserved
PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
Reserved
PCI Slave Control Register
Reserved
PCI Slave Base Address 0 Translation Register
PCI Slave Base Address 1 Translation Register
PCI Slave Base Address 2 Translation Register
PCI Slave Base Address 3 Translation Register
PCI Slave Base Address 4 Translation Register
PCI Slave Base Address 5 Translation Register
Reserved
PCI Base Address Register 0 Mirror Register
PCI Base Address Register 1 Mirror Register
PCI Base Address Register 2 Mirror Register
PCI Base Address Register 3 Mirror Register
PCI Base Address Register 4 Mirror Register
PCI Base Address Register 5 Mirror Register
Reserved
PCI Master Configuration/IO Access Data Register
PCI Master Configuration/IO Access Address Register
PCISTATSET
PCISTATCLR
-
PCIHINTSET
PCIHINTCLR
-
PCIBINTSET
PCIBINTCLR
PCIBCLKMGT
-
PCIVENDEVMIR
PCICSRMIR
PCICLREVMIR
PCICLINEMIR
PCIBAR0MSK
PCIBAR1MSK
PCIBAR2MSK
PCIBAR3MSK
PCIBAR4MSK
PCIBAR5MSK
-
PCISUBIDMIR
-
PCICPBPTRMIR
-
PCILGINTMIR
-
PCISLVCNTL
-
PCIBAR0TRL
PCIBAR1TRL
PCIBAR2TRL
PCIBAR3TRL
PCIBAR4TRL
PCIBAR5TRL
-
PCIBAR0MIR
PCIBAR1MIR
PCIBAR2MIR
PCIBAR3MIR
PCIBAR4MIR
PCIBAR5MIR
-
PCIMCFGDAT
PCIMCFGADR
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Peripheral Information and Electrical Specifications
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