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P
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 2-4. TERMINAL FUNCTIONS (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
PULLDOWN
OPER
VOLT
DESCRIPTION
SGMII0/1 and MDIO
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
3.3 V
3.3 V
SPI or UART
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
TIMER 0/1 or GPIO[8:11]
3.3 V
3.3 V
3.3 V
3.3 V
MCASP OR VIDEO PORT OR VIC
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
SGMII0RXN
SGMII0RXP
SGMII0TXN
SGMII0TXP
SGMII1RXN
SGMII1RXP
SGMII1TXN
SGMII1TXP
MDCLK
MDIO
AA10
AA9
W11
Y11
AC9
AB9
W9
W8
U9
U8
I
I
Differential SGMII port 0 RX input (negative)
Differential SGMII port 0 RX input (positive)
Differential SGMII port 0 TX output (negative)
Differential SGMII port 0 TX output (positive)
Differential SGMII port 1 RX input (negative)
Differential SGMII port 1 RX input (positive)
Differential SGMII port 1 TX output (negative)
Differential SGMII port 1 TX output (positive)
MDIO serial clock (MDCLK)
MDIO serial data (MDIO)
O
O
I
I
O
O
OZ
I/O/Z
IPD
IPU
SPICLK
SPICS1/UARTTX
SPICS2/UARTRX
SPIDI/UARTRTS
SPIDO/UARTCTS
F22
D23
F23
G23
F21
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
SPI clock output
SPI chip select 1 or UART transmit (O/Z)
SPI chip select 2 or UART receive
SPI data input or UART ready to send (O/Z)
SPI data output or UART clear to send
T0INP12/GP08
T0OUT12/GP09
T1INP12/GP10
T1OUT12/GP11
E20
D21
E21
C22
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
Timer 0 input pin for lower 32-bit counter (I) or GPIO 8
Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9
Timer 1 input pin for lower 32-bit counter (I) or GPIO 10
Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11
AHCLKR
AHCLKX
ACLKR
ACLKX
AFSR
AFSX
AXR0
AXR1
AXR2
AXR3
AXR4
AXR5
AXR6
AXR7
STCLK/AXR8
AC4
AC3
AC6
AC7
W6
AA7
AB6
Y6
AA6
AB4
Y5
V7
AA4
V6
Y7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McASP receive high-frequency master clock
McASP transmit high-frequency master clock
McASP receive master clock
McASP transmit master clock
McASP receive frame sync or left/right clock (LRCLK)
McASP transmit frame sync or left/right clock (LRCLK)
McASP data pin [0:7]
I/O/Z
The STCLK signal drives the hardware counter for use by the
video ports (I) or McASP data pin 8.
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog
converter(VDAC) output (O) or McASP data pin 9
McASP mute input
McASP mute output (O/Z).
VIDEO PORT 0 OR GPIO[12:15]
3.3 V
Video Port 0 Clock 0 (I)
3.3 V
Video Port 0 Clock 1
VDAC/AXR9
AA5
I/O/Z
IPD
3.3 V
AMUTEIN
AMUTE
AB3
U7
I/O/Z
I/O/Z
IPD
IPD
3.3 V
3.3 V
VP0CLK0
VP0CLK1
Y23
V23
I
IPU
IPU
I/O/Z
Device Overview
24
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