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P
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 3-6. PINMUX Register Field Descriptions (continued)
Bit
9:8
Field
MCASP_EN
Value
Description
Controls the pin muxing between McASP and VIC
.
UNMUXED
MUXED
(11)
STCLK, VCTL, or McASP
3-state
McASP (all McASP Pins)
(McASP without AXR8, AXR9)
ACLKR
AFSR
AXR0
AXR1
AC:LKX
AFSX
AXR2
AXR3
AHCLKR
AMUTEIN
AXR4
AXR5
AHCLKX
AMUTE
AXR6
AXR7
STCLK
VCTL
Reserved
00
01
10
11
7:6
5:4
Reserved
VLYNQ_EN
Reserved
Controls the pin muxing between Video Port 2 and VLYNQ
.
UNMUXED
(12)
VP2#1
3-state
3-state
Enable
Enable
MUXED
(13)
VP2#2 VLYNQ
3-state
3-state
00
01
10
11
VP2D12-19, VP2CLK1, VP2CTL2
VRXD0-3 and VTXD0-3, VCLK, VSCRUN
3:1
0
Reserved
TIMER_EN
Reserved
Controls the pin muxing between TIMER and GPIO[8:11]
.
MUXED
(14)
(E20, D21, E21, C22)
GPIO[8:11]
Timer 0/1
0
1
(11) The complete list of pins: AC4, AC3, AC6, AC7, W6, AA7, AB6, Y6, AA6, AB4, Y5, V7, AA4, V6, Y7, AA5, AB3, U7
(12) For the first half of the Video Port 2, the complete list of pins with function: AB1(VP2CLK0), AA1 (VP2CTL0), AB2 (VP2CTL1) and W5,
AA2, Y3, U6, Y2, W3, V5, W4 (VP2D02, VP2D03, VP2D04, VP2D05, VP2D06, VP2D07, VP2D08, VP2D09)
(13) For the second half of the Video Port 2, the complete list of pins with function: W1 (VP2CLK1/VCLK), Y1(VP2CTL2/VSCRUN), W2, V3,
V4, U1, U3, U2, U5, U4 (VP2D12/VRXD0, VP2D13/VRXD1, VP2D14/VRXD2, VP2D15/VRXD3, VP2D16/VTXD0, VP2D17/VTXD1,
VP2D18/VTXD2, VP2D19/VTXD3)
(14) The complete list of pins:E20, D21, E21, C22
Device Configuration
44
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