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2.5 Pin Assignments
2.5.1
Pin Map (Bottom View)
V
SS
D
VDD33
D
VDD33
AHCLKX
AHCLKR
ACLKR
ACLKX
V
SS
SGMII1RXN
REFCLKN
V
SS
VP2CLK0
VP2CTL1
AMUTEIN
AMUTE
V
SS
AFSR
A
VDDT
SGMII0RXP
A
VDDR
REFCLKP
VP2CTL0
VP2D07
V
SS
AXR7
AXR6
VDAC/
AXR9
AFSX
V
SS
SGMII1RXP
SGMII0RXN
V
SS
PREQ/
GP03
VP2CTL2/
VSCRUN
VP2D04
VP2D03
STCLK/
AXR8
AXR4
AXR0
V
SS
SGMII1TXP
VP2CLK1/
VCLK
VP2D12/
VRXD0
VP2D06
VP2D09
VP2D02
AXR3
V
SS
SGMII0TXP
SGMII0TXN
A
VDDA
SGMII1TXN
RSV22
V
SS
VP2D13
/VRXD1
VP2D14/
VRXD2
VP2D08
AXR5
AXR1
RSV17
VP2D15/
VRXD3
VP2D17/
VTXD1
VP2D16/
VTXD0
VP2D19/
VTXD3
VP2D18/
VTXD2
VP2D05
AXR2
MDIO
MDCLK
D
VDDD
PINTA/
GP02
PRST/
GP01
VP3CLK0/
AECLKIN
VP3CTL0/
ASDWE
VP3D05/
AED03
VP3D04/
AED02
VP3D03/
AED01
VP3D02/
AED00
V
SS
V
SS
V
SS
VP3CTL1/
ARNW
VP3D12/
AED08
VP3D09/
AED07
VP3D08/
AED06
VP3D07/
AED05
VP3D06/
AED04
AC
AB
AA
Y
W
V
U
T
R
P
N
M
V
SS
C
VDDESS
V
SS
VP3CLK1/
AECLK
OUT
VP3CTL2/
AOE
VP3D16/
AED12
VP3D15/
AED11
VP3D14/
AED10
VP3D13/
AED09
V
SS
V
SS
V
SS
V
SS
PLLV1
VP3D17/
AED13
VP3D19/
AED15
VP3D18/
AED14
V
SS
V
SS
V
SS
CLKIN1
RSV9
SYSCLK4
VP4D03/
ABE01
VP4D04/
AEA10
VP4D05
V
SS
V
SS
V
SS
C
VDD
1
2
3
4
5
6
7
8
9
10
11
12
D
VDD33
D
VDD33
D
VDD33
D
VDD33
D
VDD33
D
VDD33
D
VDD33
V
SS
RSV21
A
VDDA
C
VDD
C
VDD
C
VDD
C
VDD
D
VDD33
C
VDD
D
VDD33
D
VDD33
D
VDD33
A
VDDA
D
VDD33
V
SS
C
VDDESS
A
VDDT
V
SS
C
VDD
C
VDD
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see
Section 3.2.6
,
PINMUX Register
.
Figure 2-2
through
Figure 2-5
show the bottom view of the
ZUT
package pin assignments in four
quadrants (A, B, C, and D).
Figure 2-2. ZUT Pin Map [Top Left Quadrant]
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