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TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-35. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP0
VP1
VP2
VP3
VP4
Video Display Field 1 Image Offset
Register
0x02C0 0220
0x02C0 4220
0x02C0 8220
0x02C0 C220
0x02C1 0220
VD_IMGOFF1x
Video Display Field 1 Image Size
Register
0x02C0 0224
0x02C0 4224
0x02C0 8224
0x02C0 C224
0x02C1 0224
VD_IMGSZ1x
Video Display Field 2 Image Offset
Register
0x02C0 0228
0x02C0 4228
0x02C0 8228
0x02C0 C228
0x02C1 0228
VD_IMGOFF2x
Video Display Field 2 Image Size
Register
0x02C0 022C
0x02C0 422C
0x02C0 822C
0x02C0 C22C
0x02C1 022C
VD_IMGSZ2x
0x02C0 0230
0x02C0 4230
0x02C0 8230
0x02C0 C230
0x02C1 0230
VD_FLDT1x
Video Display Field 1 Timing Register
0x02C0 0234
0x02C0 4234
0x02C0 8234
0x02C0 C234
0x02C1 0234
VD_FLDT2x
Video Display Field 2 Timing Register
0x02C0 0238
0x02C0 4238
0x02C0 8238
0x02C0 C238
0x02C1 0238
VD_THRLDx
Video Display Threshold Register
Video Display Horizontal Synchronization
Register
0x02C0 023C
0x02C0 423C
0x02C0 823C
0x02C0 C23C
0x02C1 023C
VD_HSYNCx
Video Display Field 1 Vertical
Synchronization Start Register
0x02C0 0240
0x02C0 4240
0x02C0 8240
0x02C0 C240
0x02C1 0240
VD_VSYNS1x
Video Display Field 1 Vertical
Synchronization End Register
0x02C0 0244
0x02C0 4244
0x02C0 8244
0x02C0 C244
0x02C1 0244
VD_VSYNE1x
Video Display Field 2 Vertical
Synchronization Start Register
0x02C0 0248
0x02C0 4248
0x02C0 8248
0x02C0 C248
0x02C1 0248
VD_VSYNS2x
Video Display Field 2 Vertical
Synchronization End Register
0x02C0 024C
0x02C0 424C
0x02C0 824C
0x02C0 C24C
0x02C1 024C
VD_VSYNE2x
0x02C0 0250
0x02C0 4250
0x02C0 8250
0x02C0 C250
0x02C1 0250
VD_RELOADx
Video Display Counter Reload Register
0x02C0 0254
0x02C0 4254
0x02C0 8254
0x02C0 C254
0x02C1 0254
VD_DISPEVTx
Video Display Display Event Register
0x02C0 0258
0x02C0 4258
0x02C0 8258
0x02C0 C258
0x02C1 0258
VD_CLIPx
Video Display Clipping Register
Video Display Default Display Value
Register
0x02C0 025C
0x02C0 425C
0x02C0 825C
0x02C0 C25C
0x02C1 025C
VD_DEFVALx
0x02C0 0260
0x02C0 4260
0x02C0 8260
0x02C0 C260
0x02C1 0260
VD_VINTx
Video Display Vertical Interrupt Register
0x02C0 0264
0x02C0 4264
0x02C0 8264
0x02C0 C264
0x02C1 0264
VD_FBITx
Video Display Field Bit Register
Video Display Field 1Vertical Blanking Bit
Register
0x02C0 0268
0x02C0 4268
0x02C0 8268
0x02C0 C268
0x02C1 0268
VD_VBIT1x
Video Display Field 2Vertical Blanking Bit
Register
0x02C0 026C
0x02C0 426C
0x02C0 826C
0x02C0 C26C
0x02C1 026C
VD_VBIT2x
0x5000 0000
0x5400 0000
0x5800 0000
0x5C00 0000
0x6000 0000
Y_SRCA
Y FIFO Source Register A
0x5000 0020
0x5400 0020
0x5800 0020
0x5C00 0020
0x6000 0020
CB_SRCA
CB FIFO Source Register A
0x5000 0040
0x5400 0040
0x5800 0040
0x5C00 0040
0x6000 0040
CR_SRCA
CR FIFO Source Register A
0x5000 0080
0x5400 0080
0x5800 0080
0x5C00 0080
0x6000 0080
Y_DSTA
Y FIFO Destination Register A
0x5000 00A0
0x5400 00A0
0x5800 00A0
0x5C00 00A0
0x6000 00A0
CB_DST
CB FIFO Destination Register
0x5000 00C0
0x5400 00C0
0x5800 00C0
0x5C00 00C0
0x6000 00C0
CR_DST
CR FIFO Destination Register
0x5200 0000
0x5600 0000
0x5A00 0000
0x5E00 0000
0x6200 0000
Y_SRCB
Y FIFO Source Register B
0x5200 0020
0x5600 0020
0x5A00 0020
0x5E00 0020
0x6200 0020
CB_SRCB
CB FIFO Source Register b
0x5200 0040
0x5600 0040
0x5A00 0040
0x5E00 0040
0x6200 0040
CR_SRCB
CR FIFO Source Register B
0x5200 0080
0x5600 0080
0x5A00 0080
0x5E00 0080
0x6200 0080
Y_DSTB
Y FIFO Destination Register B
Peripheral Information and Electrical Specifications
106
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