參數(shù)資料
型號： TMX320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 61/166頁
文件大?。?/td> 1341K
代理商： TMX320DM647ZUT720
www.ti.com
P
6.3.5
DM647/DM648 Power and Clock Domains
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-3. PSC Register Memory Map (continued)
HEX ADDRESS RANGE
0x0204 6A1C
0x0204 6A20
0x0204 6A24
0x0204 6A28
0x0204 6A2C
0x0204 6A30
0x0204 6A34
0x0204 6A38
0x0204 6A3C
0x0204 6A40
0x0204 6A44
0x0204 6A48
0x0204 6A4C
0x0204 6A50
0x0204 6A54
0x0204 6A58
0x0204 6A5C
0x0204 6A60
0x0204 6A64
0x0204 6A68
0x0204 6A6C
0x0204 6A70
0x0204 6A74
0x0204 6A78
0x0204 6A7C
0x0204 6A80
0x0204 6A84
0x0204 6A8C
0x0204 6A90- 0x0204 6FFF
REGISTER ACRONYM
MDCTL7
MDCTL8
MDCTL9
MDCTL10
MDCTL11
MDCTL12
–
–
–
–
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
MDCTL29
MDCTL30
MDCTL31
–
MDCTL33
MDCTL34
–
DESCRIPTION
Module Control 7 Register (DDR2)
Module Control 8 Register (HPI)
Module Control 9 Register (VLYNQ)
Module Control 10 Register (GPIO)
Module Control 11 Register (TIMER 0)
Module Control 12 Register (TIMER 1)
Reserved
Reserved
Reserved
Reserved
Module Control 17 Register (SPI)
Module Control 18 Register (I2C)
Module Control 19 Register (PCI)
Module Control 20 Register (Video Port 0)
Module Control 21 Register (Video Port 1)
Module Control 22 Register (Video Port 2)
Module Control 23 Register (Video Port 3)
Module Control 24 Register (Video Port 4)
Module Control 25 Register (EMIFA)
Module Control 26 Register (TIMER 2)
Module Control 27 Register (TIMER 3)
Module Control 28 Register (VIC)
Module Control 29 Register (McASP)
Module Control 30 Register (UART)
Module Control 31 Register (VICP)
Reserved
Module Control 33 Register (C64x+ CPU)
Module Control 34 Register (Ethernet Subsystem)
Reserved
The DM647/DM648 includes two power domains: the System Domain and the Ethernet Subsystem
Domain. Both of these power domains are always on when the chip is on. Both of these domains are
powered by the C
VDD
pins of the DM647/DM648 device.
The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the
system peripherals such as the multichannel audio serial ports (McASPs) and the external memory
interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory
controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from
REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the
secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2
Table 6-4
provides a listing of the DM647/DM648 clock domains.
Table 6-4. DM647/DM648 Power and Clock Domains
POWER DOMAIN
System Domain
System Domain
CLOCK DOMAIN
CLKDIV1
CLKDIV3
PERIPHERAL/MODULE/USAGE
C64x+ CPU
EDMA/SCR
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Peripheral Information and Electrical Specifications
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