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參數(shù)資料
| 型號(hào)： | TMX320DM647ZUT720 |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media Processor |
| 中文描述： | 數(shù)字媒體處理器 |
| 文件頁(yè)數(shù)： | 65/166頁(yè) |
| 文件大小： | 1341K |
| 代理商： | TMX320DM647ZUT720 |
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6.4.1
PLL1 Controller Device-Specific Information
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP
device as possible. For the best performance, TI recommends that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter).The minimum CLKIN1 rise and fall times should also be observed. For the
input clock timing requirements, see
Section 6.4.4
.
As shown in
Figure 6-5
, the PLL1 controller generates several internal clocks including the system
reference clock (SYSREFCLK), and the system clocks (SYSCLK1/2/3/4/5/6). The high-frequency clock
signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves
as a reference clock for the rest of the DSP system. Dividers D1, D2, D3, D4, D5 and D6 divide the
high-frequency clock SYSREFCLK to generate SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5
and SYSCLK6, respectively.
The system clocks are used to clock different portions of the DSP as follows:
SYSCLK1 is used for the following modules 3PDMA, the SCR and the bridges, DDR Subsystem
internal logic, Video Port 0, Video Port 1, Video Port 2, Video Port 3, Video Port 4, EMIFA internal
logic.
SYSCLK2 is used for Emulation and Trace
SYSCLK3 is used for most of the peripherals. These modules are clocked from SYSCLK3: HPI, PCI,
VLYNQ, UART, I2C, TIMER 0, TIMER 1, TIMER 2, TIMER 3, SPI, McASP, VIC, GPIO, PLL Controller
1, PLL Controller 2, Config SCR
SYSCLK4 is used as the EMIFA AECLKOUT
SYSCLK5 is used as the VICP internal clock
SYSCLK6 is used as the VICP internal clock
The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE
selection on the DM647/DM648 device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are
fixed, the frequency of SYSCLK1, SYCLK3, SYSCLK5 and SYSCLK6 is tied to the frequency of
SYSREFCLK. However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of
dividers D2 and D4. For example, with PLLM in the PLL1 multiply control register set to 10011b (x20
mode) and a 35 MHz CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and
SYSCLK3 run at 233 MHz and 117 MHz, respectively. Divider D4 can be programmed through the
PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4 runs at 70 MHz.
Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, SYSCLK4, and
SYSCLK5. The PLL1 Controller must not be configured to exceed any of these constraints (certain
combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For
the PLL clocks input and output frequency ranges, see
Table 6-6
.
Table 6-6. PLL1 Clock Frequency Ranges
CLOCK SIGNAL
CLKIN1
PLLREF (PLLEN = 1)
(1)
PLLOUT
(1)
MIN
MAX
66.6
66.6
900
(2)
UNIT
MHz
MHz
MHz
33.3
400
(1)
(2)
Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register)
Only for DM648 device
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Peripheral Information and Electrical Specifications
65
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| TMX320DM647ZUT900 | Digital Media Processor |
| TMX320DM648ZUT720 | Digital Media Processor |
| TMX320DM648ZUT900 | Digital Media Processor |
| TMS320LC31PQL | DIGITAL SIGNAL PROCESSORS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TMX320DM647ZUT900 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Digital Media Processor |
| TMX320DM648ACUT7 | 制造商:Texas Instruments 功能描述:- Trays |
| TMX320DM648ACUT9 | 制造商:Texas Instruments 功能描述:- Trays |
| TMX320DM648AZUT7 | 制造商:Texas Instruments 功能描述: |
| TMX320DM648CUT7 | 制造商:Texas Instruments 功能描述:- Trays |
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