參數(shù)資料
型號(hào)： TMX320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 122/166頁
文件大?。?/td> 1341K
代理商： TMX320DM647ZUT720
www.ti.com
P
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-52. Switching Characteristics for Host-Port Interface Cycles
(1)(2)
(see
Table 6-52
through
Figure 6-38
)
-720
-900
NO.
PARAMETER
UNIT
MIN
MAX
Case 1. HPIC or HPIA read
Case 2. HPID read with no
auto-increment
(3)
Case 3. HPID read with auto-increment
and read FIFO initially empty
(3)
Case 4. HPID read with auto-increment
and data previously prefetched into the
read FIFO
5
15
9 * M + 20
Delay time, HSTROBE low to
DSP data valid
1
t
d(HSTBL-HDV)
ns
9 * M + 20
5
15
2
3
4
5
t
dis(HSTBH-HDV)
t
en(HSTBL-HD)
t
d(HSTBL-HRDYH)
t
d(HSTBH-HRDYH)
Disable time, HD high-impedance from HSTROBE high
Enable time, HD driven from HSTROBE low
Delay time, HSTROBE low to HRDY high
Delay time, HSTROBE high to HRDY high
1
3
4
ns
ns
ns
ns
15
12
12
Case 1. HPID read with no
auto-increment
(3)
Case 2. HPID read with auto-increment
and read FIFO initially empty
(3)
10 * M + 20
Delay time, HSTROBE low to
HRDY low
6
t
d(HSTBL-HRDYL)
ns
10 * M + 20
7
t
d(HDV-HRDYL)
Delay time, HD valid to HRDY low
0
ns
Case 1. HPIA write
(3)
Case 2. HPID write with no
auto-increment
(3)
5 * M + 20
Delay time, HSTROBE high to
HRDY low
34
t
d(DSH-HRDYL)
ns
5 * M + 20
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not
empty
(3)
Delay time, HAS low to HRDY high
35
t
d(HSTBL-HRDYL)
40 * M + 20
ns
36
t
d(HASL-HRDYH)
M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.
12
ns
(1)
(2)
(3)
122
Peripheral Information and Electrical Specifications
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