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參數(shù)資料
| 型號： | TMX320DM647ZUT720 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media Processor |
| 中文描述： | 數(shù)字媒體處理器 |
| 文件頁數(shù)： | 58/166頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320DM647ZUT720 |
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6.2 Recommended Clock and Control Signal Transition Behavior
6.3 Power Supplies
6.3.1
Power-Supply Sequencing
6.3.2
Power-Supply Design Considerations
6.3.3
Power-Supply Decoupling
6.3.4
Power and Sleep Controller (PSC)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
All clocks and control signals
must
transition between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit
www.ti.com/dsppower
.
The DM647/8 includes 1.2-V core supply (CVDD, CVDDESS, CVDD1, AVDDA, DVDDD, AVDDT), and
two I/O supplies—3.3-V (DVDD33) and 1.8-V (DvDD18, AVDLL1, AVDLL2, AVDDR) To ensure proper
device operation, a specific power-up sequence must be followed. Some TI power-supply devices include
features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features. For
more information on TI power supplies and their features, visit
www.ti.com/dsppower
.
Here is a summary of the power sequencing requirements:
The power ramp order must be 3.3-V (DVDD33) before 1.8-V (DvDD18, AVDLL1, AVDLL2, AVDDR),
and 1.8-V (DVDD18, AVDLL1, AVDLL2, AVDDR) before 1.2-V core supply (CVDD, CVDDESS,
CVDD1, AVDDA, DVDDD, AVDDT) —meaning during power up, the voltage at the 1.8-V rail should
never exceed the voltage at the 3.3-V rail. Similarly, the voltage at the 1.2-V rail should never exceed
the voltage at the DVDDR2 rail.
From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within
200 ms. The term "stable" means reaching the recommended operating condition (see
Section 5.2
,
Recommended Operating Conditions).
Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the DM647/8 device, the PC board should include separate power planes for core, I/O, and
ground; all bypassed with high-quality low-ESL/ESR capacitors.
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors; therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large
bulk caps (on the order of 100
F) should be furthest away, but still as close as possible. Large caps for
each supply should be placed outside of the BGA footprint.
The power and sleep controller (PSC) controls power by turning off unused power domains or by gating
off clocks to individual peripherals/modules. The DM647/DM648 devices use the clock-gating feature of
the PSC only for power savings. The PSC consists of a global PSC (GPSC) and a set of local PSCs
(LPSCs).
The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. The LPSCs for DM647/DM648 are shown in
Table 6-2
. The PSC register memory map is given in
Table 6-3
. For more details on the PSC, see the
TMS320DM647/TMS320DM648 DMP DSP Subsystem
Reference Guide
(Literature Number
SPRUEU6
).
Peripheral Information and Electrical Specifications
58
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