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參數(shù)資料
| 型號(hào)： | TMX320DM647ZUT720 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media Processor |
| 中文描述： | 數(shù)字媒體處理器 |
| 文件頁(yè)數(shù)： | 27/166頁(yè) |
| 文件大小： | 1341K |
| 代理商： | TMX320DM647ZUT720 |
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TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 2-4. TERMINAL FUNCTIONS (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
PULLDOWN
IPD
OPER
VOLT
DESCRIPTION
VP4CTL0/ABA0
J2
I/O/Z
3.3 V
Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. When
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
Video Port 4 Control 2 or Programmable synchronous address
strobe or read-enable. For programmable synchronous interface,
the r_enable field in the ChipSelect x Configuration Register
selects between ASADS and ASRE:
– If r_enable = 0, then the ASADS/ASRE signal functions as the
ASADS signal.
– If r_enable = 1, then the ASADS/ASRE signal functions as the
ASRE signal.
Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded
from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
Byte-write enables for most types of memory.
Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of
address bits or byte enables used depends on the width of
external memory. Byte-write enables for most types of memory.
Video Port 4 Data 4 or EMIFA External Address 10 (word address)
(O/Z)
Video Port 4 Data 5
Video Port 4 Data 6 or EMIFA memory space enable 2
Video Port 4 Data 7 or EMIFA memory space enable 3
Video Port 4 Data 8 or EMIFA External Address 0 (word address)
(O/Z)
Video Port 4 Data 9 or EMIFA External Address 1 (word address)
(O/Z)
Video Port 4 Data 12 or EMIFA External Address 2 (word address)
(O/Z)
Video Port 4 Data 13 or EMIFA External Address 3 (word address)
(O/Z)
Video Port 4 Data 14 or EMIFA External Address 4 (word address)
(O/Z)
Video Port 4 Data 15 or EMIFA External Address 5 (word address)
(O/Z)
Video Port 4 Data 16 or EMIFA External Address 6 (word address)
(O/Z)
Video Port 4 Data 17 or EMIFA External Address 7 (word address)
(O/Z)
Video Port 4 Data 18 or EMIFA External Address 8 (word address)
(O/Z)
Video Port 4 Data 19 or EMIFA External Address 9 (word address)
(O/Z)
EMIFA
3.3 V
EMIFA External Address 23 (word address) (O/Z)
3.3 V
EMIFA External Address 19 (word address) (O/Z)
VP4CTL1/ABA1
J1
I/O/Z
IPD
3.3 V
VP4CTL2/AADS
K2
I/O/Z
IPD
3.3 V
VP4D02/ABE00
L2
I/O/Z
IPU
3.3 V
VP4D03/ABE01
M4
I/O/Z
IPU
3.3 V
VP4D04/AEA10
M5
I/O/Z
IPU
3.3 V
VP4D05
VP4D06/ACE2
VP4D07/ACE3
VP4D08/AEA00
M6
L3
L4
L5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPD
3.3 V
3.3 V
3.3 V
3.3 V
VP4D09/AEA01
K3
I/O/Z
IPD
3.3 V
VP4D12/AEA02
K4
I/O/Z
IPD
3.3 V
VP4D13/AEA03
L6
I/O/Z
IPD
3.3 V
VP4D14/AEA04
K5
I/O/Z
IPD
3.3 V
VP4D15/AEA05
J3
I/O/Z
IPD
3.3 V
VP4D16/AEA06
J4
I/O/Z
IPD
3.3 V
VP4D17/AEA07
J5
I/O/Z
IPD
3.3 V
VP4D18/AEA08
J6
I/O/Z
IPD
3.3 V
VP4D19/AEA09
K6
I/O/Z
IPD
3.3 V
AEA23
AEA19
H4
H5
OZ
I/O/Z
IPD
IPU
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Device Overview
27
相關(guān)PDF資料 |
PDF描述 |
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| TMX320DM647ZUT900 | Digital Media Processor |
| TMX320DM648ZUT720 | Digital Media Processor |
| TMX320DM648ZUT900 | Digital Media Processor |
| TMS320LC31PQL | DIGITAL SIGNAL PROCESSORS |
| TMX320C6414TGLZ | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320DM647ZUT900 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Media Processor |
| TMX320DM648ACUT7 | 制造商:Texas Instruments 功能描述:- Trays |
| TMX320DM648ACUT9 | 制造商:Texas Instruments 功能描述:- Trays |
| TMX320DM648AZUT7 | 制造商:Texas Instruments 功能描述: |
| TMX320DM648CUT7 | 制造商:Texas Instruments 功能描述:- Trays |
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