參數(shù)資料
型號： TMX320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 153/166頁
文件大小： 1341K
代理商： TMX320DM647ZUT720
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6.19 Management Data Input/Output (MDIO)
6.19.1 MII Management Interface
6.19.2 MDIO Register Descriptions
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
REFCLKP/N Jitter and PLL Loop Bandwidth
Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby
impairing system performance. A good quality, low jitter reference clock is necessary to achieve
compliance with most if not all physical layer standards (see
Table 6-69
).
Table 6-69. REFCLKP/N Jitter Requirements for Standards Compliance
Standard
Gigabit Ethernet
Line Rate (Gbps)
1.25
Total REFCLKP/N Jitter (within PLL bandwidth)
50 ps pk-pk
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to
enumerate all PHY devices in the system. It contains two user access registers to control and monitor up
to two PHYs simultaneously.
The MDIO module implements the 802.3 serial management interface to interrogate and control two
Ethernet PHYs simultaneously using a shared two-wire bus. Figure 6-xx shows a device with two MACs,
each connected to a PHY, being managed by the MII interface module using a shared bus.
Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached
to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for
correct operation. The module is designed to allow almost transparent operation of the MDIO interface,
with very little maintenance from the core processor. Only a maximum of two PHYs may be connected at
any given time.
For more detailed information on the MDIO peripheral, see the
DM64xxx DMSoC Ethernet Media Access
Controller/Mgmt.Data Input/Output (EMAC/MDIO) Reference Guide
(literature number
SPRU851
). For a
list of supported registers and register fields, see
Table 6-70
.
Table 6-70. MDIO Registers
HEX ADDRESS RANGE
0x02D0 4000
0x02D0 4004
0x02D0 4008
0x02D0 400C
0x02D0 4010
REGISTER ACRONYM
MDIOVer
MDIOControl
MDIOAlive
MDIOLink
MDIOLinkIntRaw
DESCRIPTION
Module version register
Module control register
PHY acknowledge status register
PHY link status register
Link status change interrupt register (raw
value)
Link status change interrupt register (masked
value)
0x02D0 4014
MDIOLinkIntMasked
0x02D0 4018 - 0x02D0 401C
0x02D0 4020
Reserved
MDIOUserIntRaw
User command complete interrupt register
(raw value)
User command complete interrupt register
(masked value)
User interrupt mask set register
User interrupt mask clear register
0x02D0 4024
MDIOUserIntMasked
0x02D0 4028
0x02D0 402C
0x02D0 4030 - 0x02D0 407C
0x02D0 4080
0x02D0 4084
MDIOUserIntMaskSet
MDIOUserIntMaskClr
Reserved
MDIOUserAccess0
MDIOUserPhySel0
User access register0
User PHY select register0
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Peripheral Information and Electrical Specifications
153
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