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6.4.5
PLL1 Controller Register Description(s)
6.5 PLL2 and PLL2 Controller
PLLV2
C162
C161
EMI Filter
+1.8 V
560 pF 0.1 F
DM647/DM648
PLL2
CLKIN2
PLLM
x20
PLLOUT
PLLREF
DDR2 Memory Controller
SYSCLK1 (From PLL Controller 1)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
A summary of the PLL1 controller registers is shown in
Table 6-9
.
Table 6-9. PLL1 and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
0x020E 0000
0x020E 00E4
0x020E 0100
0x020E 0110
0x020E 0114
0x020E 011C
0x020E 0138
0x020E 013C
0x020E 0140
0x020E 0144
0x020E 0150
REGISTER NAME
PID
RSTYPE
PLLCTL
PLLM
PREDIV
PLLDIV2
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
SYSTAT
DESCRIPTION
Peripheral Identification and Revision Information Register
Reset Type Register
PLL Controller 1 Operations Control Register
PLL Controller 1 Multiplier Control Register
PLL Pre-Divider Control Register
PLL Controller 1 Control-Divider 2 Register (SYSCLK2)
PLL Controller 1 Command Register
PLL Controller 1 Status Register (Shows PLLC1 Status)
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off
Status)
PLL Controller 1 Control-Divider 4 Register (SYSCLK4)
0x020E 0160
PLLDIV4
The secondary PLL controller generates interface clocks for the DDR2 memory controller.
As shown in
Figure 6-7
, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed
to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external
PLL filter circuit must be added to PLLV2 as shown in
Figure 6-7
. The 1.8-V supply for the EMI filter must
be from the same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter
manufacturer Murata, part number NFM18CC222R1C3.
Figure 6-7. PLL Controller
All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+
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Peripheral Information and Electrical Specifications
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