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6.18.4 Ethernet Subsystem Timing
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-66. SGMII0 Registers (continued)
HEX ADDRESS RANGE
0x02D0 4848
0x02D0 484C - 0x02D0 487F
REGISTER NAME
Diag_Status
Reserved
DESCRIPTION
Diagnostics Status Register (read only)
Reserved
Table 6-67. SGMII1 Registers
HEX ADDRESS RANGE
0x02D0 4C00
0x02D0 4C04
0x02D0 4C08 - 0x02D0 4C0C
0x02D0 4C10
0x02D0 4C14
0x02D0 4C18
0x02D0 4C1C
0x02D0 4C20
0x02D0 4C24
0x02D0 4C28 - 0x02D0 4C2C
0x02D0 4C30
0x02D0 4C34
0x02D0 4C38
0x02D0 4C3C
0x02D0 4C40
0x02D0 4C44
0x02D0 4C48
0x02D0 4C4C - 0x02D0 4C7F
REGISTER NAME
IdVer
Soft_Reset
Reserved
Control
Status
Mr_Adv_Ability
Mr_Np_Tx
Mr_Lp_Adv_Ability
Mr_Np_Rx
Reserved
Reserved
Reserved
Reserved
Reserved
Diag_Clear
Diag_Control
Diag_Status
Reserved
DESCRIPTION
Identification and Version Register
Soft Reset Register
Reserved
Control Register
Status Register (read only)
Advertised Ability Register
Transmit Next Page Register
Link Partner Advertised Ability (read only)
Link Partner Receive Next Page Register (read only)
Reserved
Reserved
Reserved
Reserved
Reserved
Diagnostics Clear Register
Diagnostics Control Register
Diagnostics Status Register (read only)
Reserved
Table 6-68. Ethernet Subsystem Timing Requirements
UNIT
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ps
ns
μ
s
PARAMETER
MIN
NOM
MAX
t
01
REFCLKP/N period, X4 mode
x 5 mode
x 6 mode
x 8 mode
x 10 mode
x 12 mode
x 12.5 mode
x 15 mode
x 20 mode
x 25 mode
REFCLKP/N duty cycle
REFCLKP/N rise/fall
PLL Clock Period, x
n
Mode
PLL power up
2.35
2.35
2.82
3.76
4.7
5.65
5.88
7.06
9.41
11.76
40
4
5
6
8
10
12
12.5
15
30
35
60
t
02
t
03
t
04
t
05
700
t
o1
/
n
1
Peripheral Information and Electrical Specifications
152
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