參數(shù)資料
型號: TMX320DM647ZUT720
廠商: Texas Instruments, Inc.
英文描述: Digital Media Processor
中文描述: 數(shù)字媒體處理器
文件頁數(shù): 19/166頁
文件大?。?/td> 1341K
代理商: TMX320DM647ZUT720
www.ti.com
P
2.6 Terminal Functions
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The terminal functions tables (
Table 2-4
through
Table 2-5
) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see
Section 3
.
All device boot and configuration pins are multiplexed with functional pins. These pins function as device
boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on
reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins
are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be
pulled up/down to the desired value via an external resistor.
Table 2-4. TERMINAL FUNCTIONS
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
PULLDOWN
OPER
VOLT
DESCRIPTION
Clock/PLL Configuration
3.3 V
3.3 V
CLKIN1
CLKIN2
REFCLKN
REFCLKP
PLLV1
PLLV2
SYSCLK4
M1
F1
AC11
AB11
N3
G7
M3
I
I
I
I
IPD
IPD
Clock Input for PLL1
Clock Input for PLL2
Differential Reference Clock input (negative) for SGMII
Differential Reference Clock input (positive) for SGMII
1.8-V I/O Supply Voltage for PLL1
1.8-V I/O Supply Voltage for PLL2
Clock out of device speed/4
JTAG
3.3 V
JTAG Test Port Clock
3.3 V
JTAG Test Port Data In
3.3 V
JTAG Test Port Data Out
3.3 V
JTAG Test Port Mode Select
3.3 V
JTAG Test Port Reset
3.3 V
JTAG Test Port Emulation 0
3.3 V
JTAG Test Port Emulation 1
3.3 V
JTAG Test Port Emulation 2
3.3 V
JTAG Test Port Emulation 3
3.3 V
JTAG Test Port Emulation 4
3.3 V
JTAG Test Port Emulation 5
3.3 V
JTAG Test Port Emulation 6
3.3 V
JTAG Test Port Emulation 7
3.3 V
JTAG Test Port Emulation 8
3.3 V
JTAG Test Port Emulation 9
3.3 V
JTAG Test Port Emulation 10
3.3 V
JTAG Test Port Emulation 11
RESET/INTERRUPTS
3.3 V
Non maskable Interrupt
3.3 V
Reset Status Pin
3.3 V
Device Reset
3.3 V
Power On Reset
A
A
1.8 V
1.8 V
3.3 V
I/O/Z
IPD
TCLK
TDI
TDO
TMS
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
H23
J22
J23
L22
L23
K23
K22
K21
K20
L18
J21
K19
H21
J20
H20
J19
K18
I
I
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
OZ
I
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
NMI
RESETSTAT
RESET
POR
J18
H19
G20
H18
I
IPD
O
I
I
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or GPIO[0:7]
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