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P
3.2.2
DSPBOOTADDR Register Description
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Figure 3-1. BOOTCFG Register
31
24
Reserved
R-0
23
22
21
20
19
18
17
16
AECLKINSEL
PC166
HPIWIDTH
Reserved
FASTBOOT
Reserved
DUHPIEN
EMIFAWIDTH
R-L
R-1
R-L
R-1
R-L
R-L
15
8
Reserved
7
4
3
0
Reserved
BOOTMODE
R-0
R-L
LEGEND: R/W = Read/Write; R = Read only; L = latched; -
n
= value after reset
Table 3-2. BOOTCFG Register Field Descriptions
Bit
31:24
23
Field
Reserved
AECLKINSEL
Value
Description
Reserved
Controls the clock input for EMIFA. Latched from AECLKINSEL at RESET or POR deassertion
EMIFA clocked from internal SYSCLK
EMIFA clocked from outside from AECLKIN
Controls PCI speed. PCI. Latched from PCI66 at RESET or POR deassertion
33 MHz PCI
66 MHz
Controls HPI bus width. Latched from HPIWIDTH at RESET or POR deassertion
16 bit
32 bit
Reserved
Fast Boot. Latched from FASTBOOT at RESET or POR deassertion
No Fast Boot
Fast Boot
Reserved
PCI Enable Default. Latched from UHPIEN at RESET or POR deassertion
UHPI disabled
UHPI enabled
EMIFA CS2 Bus Width Default. Latched from EMIFAWIDTH at RESET or POR deassertion
8-bit
16-bit
Reserved
Boot Mode. Latched from BOOTMOD at RESET or POR deassertion
1
0
22
PCI66
0
1
21
HPIWIDTH
0
1
1
20
19
Reserved
FASTBOOT
0
1
18
17
Reserved
DUHPIEN
0
1
16
EMIFAWIDTH
0
1
15:4
3:0
Reserved
BOOTMODE
The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register
format is shown in
Figure 3-2
and bit field descriptions are shown in
Table 3-3
. DSPBOOTADDR is
readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the
default of the DSPBOOTADDR Register. It can default to either the base address of L2 ROM
(0x00800000) or the base address of EMIFA CS2 (0xA0000000)
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Device Configuration
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