參數(shù)資料
型號： TMX320DM647ZUT720
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 103/166頁
文件大小： 1341K
代理商： TMX320DM647ZUT720
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P
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
ASADS/ASRE
(B)
AAOE/ASOE
(B)
AAWE/ASWE
(B)
A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).
In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
BE1
BE2
BE3
BE4
Q1
Q2
Q3
Q4
12
11
3
1
12
10
4
2
1
8
5
8
EA1
EA2
EA3
EA4
10
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
ASADS/ASRE
(B)
AAOE/ASOE
(B)
AAWE/ASWE
(B)
BE1
BE2
BE3
BE4
Q1
Q2
Q3
11
3
12
10
4
2
1
8
5
8
EA1
EA2
10
EA3
EA4
Write
Latency =
1
(B)
1
Q4
12
A The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).
In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
B AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Figure 6-19. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)
(A)
Figure 6-20. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1)
(A)
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Peripheral Information and Electrical Specifications
103
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