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TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Table 6-4. DM647/DM648 Power and Clock Domains (continued)
POWER DOMAIN
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
Ethernet Subsystem Domain
CLOCK DOMAIN
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV4 0
CLKDIV4 1
CLKDIV4 2
CLKDIV2
SerDes TXBCLK
PERIPHERAL/MODULE/USAGE
TSIP0
TSIP1
DDR Subsystem
Video Port 0
Video Port 1
Video Port 2
Video Port 3
Video Port 4
EMIFA
HPI
PCI
VLYNQ
UART
I2C
TIMER 0
TIMER 1
TIMER 2
TIMER 3
SPI
McASP
VIC
GPIO
PLL Controller 1
PLL Controller 2
Config SCR
Internal EMIFA Clock
Emulation and Trace
VICP cop_clk/2
VICP cop_clk
Ethernet Subsystem
The DM647/DM648 architecture is divided into the power and clock domains shown in
Table 6-5
, which
further shows the clock domains and their ratios.
Table 6-5. DM647/DM648 Clock Domain Assignment
SUBSYSTEM
CLOCK DOMAIN
DOMAIN CLOCK SOURCE
FIXED RATIO VS SYSREFCLK
FREQUENCY
-
1:3
1:4
1:6
1:4
1:4
1:2
DSP Subsystem
Peripherals (CLKDIV3 Domain)
Emulation/Trace
Peripherals (CLKDIV6 Domain)
Internal EMIFA Clock
VICP cop_clk/2
VICP cop_clk
CLKDIV1
CLKDIV3
CLKDIV4 1
CLKDIV6
CLKDIV4 0
CLKDIV4 2
CLKDIV2
PLLC1.REFSYSCLK
PLLC1.SYSCLK1
PLLC1.SYSCLK2
PLLC1.SYSCLK3
PLLC1.SYSCLK4
PLLC1.SYSCLK5
PLLC1.SYSCLK6
Peripheral Information and Electrical Specifications
62
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