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6.13 Universal Asynchronous Receiver/Transmitter (UART)
6.13.1 UART Peripheral Register Description(s)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The DM647/DM648 devices have a UART peripheral. The UART has the following features:
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Frequency pre-scale values from 1 to 65, 535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
5, 6, 7, or 8-bit characters
–
Even, odd, or no parity bit generation and detection
–
1, 1.5, or 2 stop bit generation
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
Loopback controls for communications link fault isolation
–
Break, parity, overrun, and framing error simulation
Modem control functions (CTS, RTS).
The UART registers are listed in
Table 6-44
.
Table 6-44. UART Register Descriptions
HEX ADDRESS RANGE
0x0204 7000
0x0204 7000
0x0204 7004
0x0204 7008
0x0204 7008
0x0204 700C
0x0204 7010
0x0204 7014
0x0204 7018
0x0204 701C
0x0204 7020
0x0204 7024
0x0204 7028
0x0204 702C
0x0204 7030
0x0204 7034 - 0x0204 73FF
ACRONYM
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
-
-
DLL
DLH
PID1
PID2
PWREMU_MGMT
-
REGISTER NAME
UART Receiver Buffer Register (Read Only)
UART Transmitter Holding Register (Write Only)
UART Interrupt Enable Register
UART Interrupt Identification Register (Read Only)
UART FIFO Control Register (Write Only)
UART Line Control Register
UART Modem Control Register
UART Line Status Register
Reserved
Reserved
UART Divisor Latch (LSB)
UART Divisor Latch (MSB)
Peripheral Identification Register 1
Peripheral Identification Register 2
UART Power and Emulation Management Register
Reserved
Peripheral Information and Electrical Specifications
114
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